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1、1|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Virtual ConferenceSeptember 28-29,2021SoC Construction Using UCIeTM(Universal Chiplet Interconnect ExpressTM):A Game ChangerPresented by:Dr.Debendra Das SharmaIntel Senior Fellow and co-GM,Memory and I/O Tech
2、nologiesUCIe Consortium Chairman2|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023AgendaUCIe Consortium OverviewOn-Package Interconnects:Opportunities and ChallengesUniversal Chiplet Interconnect Express(UCIe):An Open Standard for ChipletsIntroducing UCIe 1.
3、1 UCIe Usage ModelsFuture Directions and Conclusions 3|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Board MembersLeaders in semiconductors,packaging,IP suppliers,foundries,and cloud service providers are joining together to drive The open chiplet ecosyste
4、m.JOIN US!3120+Member Companies and Growing!4|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe Consortium is Open for Membership UCIe Consortium welcomes interested companies and institutions to join the organization at the Contributor and Adopter level.
5、UCIe Consortium was founded in March 2022,incorporated in June 2022.Two levels of memberships:Contributor and Adopter Contributor Membership Access the Final Specifications(ex:1.0,1.1,2.0,etc.)Implement with the IP protections as outlined in the Agreements Right to attend Corporation trade shows or
6、other industry events as determined by the Board Participate in the technical working groups Influence the direction of the technology Access the intermediate(dot level)specifications Election to get to the Promoter Class/Board every year when the term of half the board completes Adopter Membership
7、Access the Final Specifications(ex:1.0,1.1,2.0,etc.),but not intermediate level specifications Implement with the IP protections as outlined in the Agreements Right to attend Corporation trade shows or other industry events as determined by the Board5|2023 Storage Developer Conference.UCIe Consortiu
8、m.All Rights Reserved.On-Package Interconnects:Opportunities and Challenges6|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Moore Predicted“Day of Reckoning”“It may prove to be more economical to build large systems out of smaller functions,which are separa
9、tely packaged and interconnected.”*-Gordon E.Moore*“Cramming more components onto integrated circuits,”Electronics,Volume 38,Number 8,April 19,19657|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Drivers for On-Package Chiplets Reticle Limit,yield optimizat
10、ion,scalable performance Same dies on package(Scale-up)Increasing design costs at leading edge process nodes Disaggregate dies across different nodes Deploy latest process node for advanced functionality Time to Market (Late binding)Easily enables Custom silicon for different customers leveraging a
11、common base product E.g.,Different acceleration functions with common compute Different process nodes optimized for different functions E.g.,Memory,logic,analog,co-packaged optics Enables high,power-efficient bandwidth with low-latency access(e.g.,HBM memory)Source:IBS(as cited in IEEE Heterogeneous
12、 Integration Roadmap)8|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Components of Chiplet Interoperability Chiplet Form FactorDie Size/bump locationPower delivery SoC Construction(Application Layer)Reset and InitializationRegister accessSecurity Die-to-Di
13、e Protocols(Data Link to Transaction Layer)PCIe/CXL/Streaming Plug and play IPs Die-to-Die I/O(Physical Layer)Electrical,bump arrangement,channel,reset,initialization,power,latency,test repair,technology transition Die-to-Die I/ODie(Chiplet)ProtocolDie-to-Die I/OProtocolDie(Chiplet)ChipDie-to-DieI/O
14、Die-to-DieProtocolChipletForm FactorSoC Construction(Example SoC showing two chiplets only)9|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Design Choice:Seamless Integration from Node Package On-die Enables Reuse,Better User ExperienceNode/Board LevelInteg
15、rationCPUCPUAcceleratorI/O TileMemMemMemMemCXL/PCIe/CPU-CPU(Electrical/Optical/)DDRPackage Level Integration(with on-package interconnects)On-die IntegrationSame Software,IP,and Subsystem to build scalable solutions offers economies of scale,time to market advantage,and seamless user experience.Inno
16、vations at the open slot in board level needs to migrate to package level for multiple usages!10|2023 Storage Developer Conference.UCIe Consortium.All Rights Reserved.UCIe(Universal Chiplet Interconnect Express):An Open Standard for ChipletsGuiding Principles of UCIe1.Open ecosystem with plug-and-pl
17、ay2.Backward compatible evolution when appropriate to ensure investment protection3.Best power,performance,and cost metrics across the industry applicable across the entire compute continuum4.Continuously innovate to meet the needs of evolving compute landscape(Leveraging decades of experience drivi
18、ng successful industry standards at the board level:PCIe,CXL,USB,etc.)11|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Enables construction of SoCs that exceed maximum reticle size Package becomes new System-on-a-Chip(SoC)with same dies(Scale Up)Reduces ti
19、me-to-solution(e.g.,enables die reuse)Lowers portfolio cost(product&project)Enables optimal process technologies Smaller(better yield)Reduces IP porting costs Lowers product SKU costEnables a customizable,standard-based product for specific use cases(bespoke solutions)Scales innovation(manufacturing
20、/process locked IPs)Align Industry Around an Open Platform to Enable Chiplet Based SolutionsOPEN CHIPLET:PLATFORM ON A PACKAGEHigh-Speed StandardizedChip-to-Chip Interface(UCIe)Customer IP&Customized ChipletsSea of Cores(heterogeneous)Advanced 2D/2.5D/3D PackagingHeterogeneous Integration Fueled by
21、an Open Chiplet Ecosystem(Mix-and-match chiplets from different process nodes/fabs/companies/assembly)11Motivation20X I/O Performance at 1/20th Power vs off-package SerDes at LaunchGap more prominent with better on-package technologies in futureMemory12|2023 SNIA.All Rights Reserved.Property of Univ
22、ersal Chiplet Interconnect Express(UCIe)2023UCIe-Architected and specified from the ground-up to deliver the best KPIs while meeting wide adoption criteria to drive innovations at package levelKey Technology Metrics Bandwidth density(linear&area)Data Rate&Bump Pitch Energy Efficiency(pJ/b)Scalable e
23、nergy consumption Low idle power(entry/exit time)Latency(end-to-end:Tx+Rx)Channel Reach Technology,frequency,&BER Reliability&Availability Cost(Standard vs advanced packaging)Key Metrics and Adoption CriteriaFactors Affecting Wide Adoption Interoperability Full-stack,plug-and-play with existing s/w
24、is+Different usages/segments Technology Across process nodes&packaging options Power delivery&cooling Repair strategy(failure/yield improvement)Debug controllability&observability Broad industry support/Open ecosystem Learnings from other standards efforts13|2023 SNIA.All Rights Reserved.Property of
25、 Universal Chiplet Interconnect Express(UCIe)2023UCIe 1.0 Specification Layered Approach with industry-leading KPIs Physical Layer:Die-to-Die I/O Die to Die Adapter:Reliable delivery Support for multiple protocols:bypassed in raw mode Protocol:CXL/PCIe and Streaming CXL/PCIe for volume attach and pl
26、ug-and-playSoC construction issues are addressed w/CXL/PCIe CXL/PCIe addresses common use casesI/O attach,Memory,Accelerator Streaming for other protocolsScale-up(e.g.,CPU/GP-GPU/Switch from smaller dies)Protocol can be anything(e.g.,AXI/CHI/SFI/CPI/etc)Raw Mode only Well defined specification:inter
27、operability and future evolution Configuration register for discovery and run-timecontrol and status reporting in each layertransparent to existing drivers Form-factor and Management Compliance for interoperability Plug-and-play IPs with RDI/FDI interfaceDIE-TO-DIE ADAPTERPHYSICAL LAYERFORM FACTORPR
28、OTOCOL LAYERPCIe,CXL,Streaming(e.g.,AXI,CHI,symmetric coherency,memory,etc)Flit-Aware Die-to-Die Interface(FDI)Raw Die-to-Die Interface(RDI)Link TrainingLane Repair/Reversal(De)ScramblingAnalog Front end/ClockingSideband,Config RegistersChannelArb/Mux(if multiple protocols)CRC/Retry(when applicable)
29、Link state managementParameter negotiationConfig Registers(Bumps/Bump Map)Scope of UCIe SpecificationRaw Mode(bypass D2D Adapter to RDI e.g.,SERDES to SoC)14|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023One UCIe 1.0 spec supports different flavors of pack
30、aging options to build an open ecosystemUCIe 1.0:Supports Standard and Advanced Packages(Standard Package)(Advanced Package Choice Examples)Die-2Package SubstrateDie-0Die-1Die-2Package SubstrateDie-0Die-1Silicon Bridge(e.g.EMIB)Silicon Bridge(e.g.EMIB)Die-2Die-0Package SubstrateInterposer(e.g.CoWoS)
31、Die-1Standard Package:2D cost effective,longer distanceAdvanced Packages:2.5D power-efficient,high bandwidth density Dies can be manufactured anywhere and assembled anywhere can mix 2D and 2.5D in same package Flexibility for SoC designer15|2023 SNIA.All Rights Reserved.Property of Universal Chiplet
32、 Interconnect Express(UCIe)2023UCIe PHY:Bump-Out for Interoperability UCIe architected with process portability in mindCircuit components can be built with common digital/analog structures Bump-out specified in the specification for interoperability even with future bump-pitch reductionsDie rotation
33、 and mirroring supportedFixed beachfront allows forMulti-generational compatibilityAs bump pitches decreaseFoCoS orrxcksbRDrxcksb vcciorxdatasbrxdatasbRDtxdatasbRDtxdatasbvcciotxcksb txcksbRDrxdata50rxdata35rxdata29rxdata14rxdataRD0rxdataRD3rxdata49rxdata34rxdata28rxdata13rxdata51rxdata36rxdata30rxd
34、ata15vssrxdata63vcciorxdata33vcciorxdata12rxdata52vssrxdata31vssrxdata0vssrxdata48rxdata32rxdata27rxdata11rxdata53rxdata37rxdataRD1rxdata16rxdata1rxdata62rxdata47rxdataRD2rxdata26rxdata10rxdata54rxdata38vssrxdata17vssrxdata61rxdata46vcciorxdata25rxdata9rxdata55rxdata39rxckRDrxdata18rxdata2vssrxdata4
35、5rxvldRDrxdata24rxdata8rxdata56vssrxckn rxdata19rxdata3rxdata60rxdata44rxvld vssrxdata7rxdata57rxdata40rxckp rxdata20vssrxdata59rxdata43rxtrkrxdata23rxdata6rxdata58rxdata41vssrxdata21rxdata4vssrxdata42vcciorxdata22rxdata5vcciovcciovcciovcciovcciovcciotxdata21vcciotxdata41txdata58txdata5txdata22vsstx
36、data42vsstxdata4txdata20txckp txdata40txdata57txdata6txdata23txtrktxdata43txdata59vsstxdata19txckn vsstxdata56txdata7vsstxvld txdata44txdata60txdata3txdata18txckRD txdata39txdata55txdata8txdata24txvldRDtxdata45vsstxdata2txdata17vcciotxdata38txdata54txdata9txdata25vsstxdata46txdata61vcciovcciovcciovc
37、ciovcciotxdata10txdata26txdataRD2txdata47txdata62txdata1txdata16txdataRD1txdata37txdata53txdata11txdata27txdata32txdata48vsstxdata0vsstxdata31vsstxdata52txdata12vsstxdata33vsstxdata63vsstxdata15txdata30txdata36txdata51txdata13txdata28txdata34txdata49txdataRD3txdataRD0txdata14txdata29txdata35txdata50
38、vcciovcciovcciovcciovcciovcciovcciovcciovcciovcciotxdatasbtxcksbvccaonvccaonrxcksbrxdatasbvcciovcciovcciovcciovcciovcciovssvssvcciovssvssvssvsstxdata7txdata9vssrxdata8rxdata6txdata5txckntxdata11rxdata10rxckprxdata4vsstxdata6txdata8vssrxdata9rxdata7txdata4txckptxdata10rxdata11rxcknrxdata5vcciovssvssv
39、cciovssvsstxdata1txvldtxdata15rxdata14rxtrkrxdata0vcciotxdata3txdata13vcciorxdata12rxdata2txdata0txtrktxdata14rxdata15rxvldrxdata1vsstxdata2txdata12vssrxdata13rxdata3m2rxdatasbm2rxcksbvccaonm2txcksbm2txdatasbvccaonm1txdatasbm1txcksbvccaonvccaonm1rxcksbm1rxdatasbvcciovcciovcciovcciovcciovcciovssvssvs
40、svssvssvssm2rxdata6m2rxdata8vssm2txdata9m2txdata7vssm2rxdata4m2rxckpm2rxdata10m2txdata11m2txcknm2txdata5m2rxdata7m2rxdata9vssm2txdata8m2txdata6vssm2rxdata5m2rxcknm2rxdata11m2txdata10m2txckpm2txdata4vssvssvssvssvssvssm2rxdata0m2rxtrkm2rxdata14m2txdata15m2txvldm2txdata1m2rxdata2m2rxdata12vssm2txdata13
41、m2txdata3vssm2rxdata1m2rxvldm2rxdata15m2txdata14m2txtrkm2txdata0m2rxdata3m2rxdata13vcciom2txdata12m2txdata2vcciovcciovcciovcciovcciovcciovcciovssvssvcciovssvssvcciovssm1txdata7m1txdata9vssm1rxdata8m1rxdata6m1txdata5m1txcknm1txdata11m1rxdata10m1rxckpm1rxdata4vssm1txdata6m1txdata8vssm1rxdata9m1rxdata7
42、m1txdata4m1txckpm1txdata10m1rxdata11m1rxcknm1rxdata5vcciovssvssvcciovssvssm1txdata1m1txvldm1txdata15m1rxdata14m1rxtrkm1rxdata0vcciom1txdata3m1txdata13vcciom1rxdata12m1rxdata2m1txdata0m1txtrkm1txdata14m1rxdata15m1rxvldm1rxdata1vssm1txdata2m1txdata12vssm1rxdata13m1rxdata3(UCIe-S Unstacked Bump-out)(UC
43、Ie-S Stacked Bump-out)(UCIe-A Bump-out)16|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Physical Layer(Single Module Configuration)(Two Module Configuration)(Four Module Configuration)(4-Module Configuration with UCIe)N=16 for StandardN=64 for Advanced Uni
44、t is One Module:uni-directional:1,2,or 4 modules form a Link 16(64)SE Lanes for Std(Adv)1 SE Lane of valid 1 differential pair of forwarded clock 1 lane(SE)calibration-Track Lane reversal on Transmit side Reliability:Spare Lanes in Adv;degradation in Std Supported frequencies:4,8,12,16,24,32 GHz A c
45、omponent must support all data rates up to its advertised maximum data rate for interoperability B/W per module/dir:64 GB/s Std,256 GB/s Adv:Two module gets 2X,4-module gets 4X Sideband:always on;2 Lanes/direction 800 MHz data and clock Used for training,debug,management,etc;Leverages depopulated bu
46、mps to ensure no extra shore-line Valid used for effective dynamic power management17|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023D2D Adapter and Flit Mapping Through FDI Responsible for packetizationAdds Flit Header(2B)and CRC(2B)Supported Flit Sizes:68
47、B and two flavors of 256BDecided at negotiation Flit Hdr(2B):Protocol ID(3b),Credit(1b),Flit Ack/Nak management(2b command+8b sequence number),Rsvd(2b)CRC:Covers 128B payload(smaller payloads are 0-extended)Triple bit flip detection guarantee with 16 bitsReplay if CRC failsSample RTL code for CRC pr
48、ovided in the spec(a.68-Byte Flit usage CXL 2.0/PCIe Non-Flit Mode/Streaming)(b.256-Byte Flit usage CXL 3.0/PCIe 6.0)Flit Hdr(2B)CRC0(2B)CRC1(2B)Flit Hdr(2B)Flit Hdr(2B)CRC(2B)62B of Flit 12B of Flit 158B of Flit 2 or all 0s if no Flit from Protocol LayerByte 064Byte 064128192(4B)DLP/Flit Chunk 362B
49、 of Flit Chunk 064B of Flit Chunk 164B of Flit Chunk 246 B of Flit Chunk 310B Rsvd/Opt Flit1(Opt Flit is for better link efficiency to use the unused CRC/FEC bytes in PCIe/CXL)Flit Hdr(2B)CRC0(2B)(DLP 2.5/4B Rsvd/Opt Flit2)CRC1(2B)(10B Rsvd/Opt Flit3)Byte 064128192(c.256-Byte Latency-Optimized Flit
50、usage CXL 3.0/Streaming)18|2023 Storage Developer Conference.UCIe Consortium.All Rights Reserved.UCIe 1.1:Backward-Compatible to UCIe 1.0Enhancements for Automotive Segment UsageNew Usages:Streaming Protocols with Full Stack Cost Optimization for Advanced PackagingEnhancements for Compliance Testing
51、19|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe 1.1:Automotive Enhancements Automotive is an important segment of the compute continuum Announcing the formation of an Automotive WG to explore enhancing UCIe for automotive usages Automotive moving tow
52、ards UCIe based chiplets to leverage the broad ecosystem UCIe is a compelling technology for automotive compute needs.UCIe 1.1 has the following enhancements building on UCIe 1.0:Preventive Monitoring for link healthRun-time testability of failure rate of the linkField repairability to get around fa
53、ults20|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe 1.1:Automotive Enhancements Preventive Monitoring:Added new registers to capture Eye Margin(eye width and eye height,if applicable)information in a standard format from trainingSW can trigger period
54、ic retrain of the link to get eye margin info using existing UCIe 1.0 mechanism Run-time Testability of Link HealthExisting mechanism in UCIe 1.0:Periodic parity Flit injection and checking for monitoring health of each Lane in mission modeEnhancements in UCIe 1.1:Per-Lane error Log/counter with abi
55、lity to send interruptUsage:Software can inject periodic parity Flit and monitor the UCIe 1.1 error log register to assess the health of each Lane to assess the Link health and repair if needed Field RepairabilityAlready present with UCIe 1.0(mask Lane,retrain,etc)so no changes in this area We will
56、continue to monitor and meet the automotive needs21|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe 1.1:Streaming Protocols on Full Stack UCIe 1.0 supports Streaming Protocol(e.g.,AXI,CHI,SMP coherency protocols,SFI,CPI)only in Raw Mode Two enhancements
57、 with UCIe 1.1(raw mode still supported)1.Streaming Protocols can use the D2D adapter Enables them to reuse the CRC,Retry etc.Mechanism:map streaming to existing Flit Formats at FDI interface2.Streaming Protocols can multiplex with other protocols with on-demand interleaving Enables co-existence of
58、multiple protocols(e.g.,streaming for processing,PCIe for discovery,DMA,TLB,error reporting,interrupt,etc.)for different use cases Mechanism:Protocol muxing for Streaming protocol with existing Flit Formats at FDI interfaceDIE-TO-DIE ADAPTERPHYSICAL LAYERFORM FACTORPROTOCOL LAYERPCIe/CXL/StreamingFD
59、IRaw Die-to-Die Interface(RDI)(Bumps/Bump Map)Scope of UCIe 1.1 SpecificationPROTOCOL LAYERPCIe/CXL/StreamingStack MuxFlit-Aware Die-to-Die Interface(FDI)Raw Mode22|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe 1.1:Streaming Protocol Flit FormatsForma
60、t NumberFlit Format NamePCIe Non-Flit ModePCIe Flit ModeCXL 68B Flit ModeCXL 256B Flit ModeStreamingUCIe 1.0UCIe 1.11RawOptionalOptionalOptionalOptionalMandatory268BMandatoryN/AMandatoryN/AN/ASupported3Standard 256B End HeaderN/AMandatoryN/AN/AN/ASupported4Standard 256B Start HeaderN/AOptionalN/AMan
61、datoryN/ASupported5Latency Optimized 256B without optional bytesN/AN/AN/AOptionalN/ASupported6Latency Optimized 256B with optional bytesN/AStrongly RecommendedN/AStrongly RecommendedN/ASupported23|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)202311
62、0vssvssvcciovcciovcciovcciovssvss29vssvssvcciovcciovcciovcciovssvss28vssrxcksbRDrxcksb vssrxdatasbrxdatasbRDvssvss27vsstxdatasbRDtxdatasbvssvsstxcksb txcksbRDvss26rxdata54rxdata50rxdata35vssrxdata29rxdata14rxdata11rxdataRD025vssrxdata52rxdata49rxdata34rxdataRD1rxdata28rxdata13rxdata924rxd
63、ata55rxdata51rxdata36rxdataRD2rxdata30rxdata15rxdata10vss23rxdataRD3rxdata53rxdata48rxdata33vssrxdata27rxdata12rxdata822rxdata61vssrxdata37vssrxdata31rxdata16vssrxdata021rxdata63rxdata56rxdata47rxdata32rxckRDrxdata26rxdata17rxdata220rxdata60rxdata46vssrxvldRDrxdata25vssrxdata7vss19vssrxdata57rxdata4
64、3rxdata38rxcknrxdata23rxdata18rxdata318rxdata59rxdata45rxdata40rxvldvssrxdata20rxdata6rxdata117rxdata62rxdata58rxdata42rxdata39rxckprxdata22rxdata19rxdata416vssrxdata44rxdata41rxtrkrxdata24rxdata21rxdata5vss15vccfwdiovccfwdiovccfwdiovccfwdiovccfwdiovccfwdiovccfwdiovccfwdio14vcciovcciovcciovcciovccio
65、vcciovcciovccio13vsstxdata5txdata21txdata24txtrktxdata41txdata44vss12txdata4txdata19txdata22txckp txdata39txdata42txdata58txdata6211txdata1txdata6txdata20vsstxvld txdata40txdata45txdata5910txdata3txdata18txdata23txckn txdata38txdata43txdata57vss9vsstxdata7vsstxdata25txvldRDvsstxdata46txdata608txdata
66、2txdata17txdata26txckRDtxdata32txdata47txdata56txdata637txdata0vsstxdata16txdata31vsstxdata37vsstxdata616txdata8txdata12txdata27vsstxdata33txdata48txdata53txdataRD35vsstxdata10txdata15txdata30txdataRD2txdata36txdata51txdata554txdata9txdata13txdata28txdataRD1txdata34txdata49txdata52vss3txdataRD0txdat
67、a11txdata14txdata29vsstxdata35txdata50txdata542vcciovcciovcciovcciovcciovcciovcciovccio1vcciovcciovcciovcciovcciovcciovcciovccio1234567857vssvcciovcciovss56vssvcciovcciovss55vssvcciovcciovss54rxcksbRDrxcksb rxdatasbrxdatasbRD53txdatasbRDtxdatasbtxcksb txcksbRD52rxdata50rxdata36rxdata14rxdataRD051rxd
68、ataRD3rxdata49rxdata27rxdata1350rxdata51rxdata35rxdata15rxdata049vssrxdata48vssrxdata1248rxdata52rxdata34rxdata16vss47rxdata63vssrxdata28rxdata1146rxdata53rxdata33rxdata17rxdata145rxdata62rxdata47rxdata29rxdata1044vcciovcciovcciovccio43rxdata61rxdata46rxdata30vss42vssvssrxdata26rxdata241rxdata60rxda
69、ta37rxdata31rxdata940rxdata54rxdata32rxdata25rxdata339rxdata59rxdata38rxdataRD1rxdata838rxdata55rxdataRD2rxdata24rxdata437vssrxdata39vssvss36rxdata45vssrxdata23rxdata735rxdata56rxdata40rxckRDrxdata1834vssrxvldRDrxdata22vss33rxdata57rxdata41rxcknrxdata1932rxdata44rxvldvssrxdata631rxdata58vssrxckprxda
70、ta2030rxdata43rxtrkrxdata21rxdata529vssrxdata42vssvss28vccfwdiovccfwdiovccfwdiovccfwdio27vcciovcciovcciovccio26vssvsstxdata42vss25txdata5txdata21txtrktxdata4324txdata20txckp vsstxdata5823txdata6vsstxvldtxdata4422txdata19txckn txdata41txdata5721vsstxdata22txvldRDvss20txdata18txckRDtxdata40txdata5619t
71、xdata7txdata23vsstxdata4518vssvsstxdata39vss17txdata4txdata24txdataRD2txdata5516txdata8txdataRD1txdata38txdata5915txdata3txdata25txdata32txdata5414txdata9txdata31txdata37txdata6013txdata2txdata26vssvss12vsstxdata30txdata46txdata6111vcciovcciovcciovccio10txdata10txdata29txdata47txdata629txdata1txdata
72、17txdata33txdata538txdata11txdata28vsstxdata637vsstxdata16txdata34txdata526txdata12vsstxdata48vss5txdata0txdata15txdata35txdata514txdata13txdata27txdata49txdataRD33txdataRD0txdata14txdata36txdata502vcciovcciovcciovccio1vcciovcciovcciovccio45vssvssvcciovcciovss44vssvcciovcciovssvss43vssvss
73、vcciovcciovss42rxcksbRDrxcksb vcciorxdatasbrxdatasbRD41txdatasbRDtxdatasbvcciotxcksb txcksbRD40rxdata50rxdata35rxdata29rxdata14rxdataRD039rxdataRD3rxdata49rxdata34rxdata28rxdata1338rxdata51rxdata36rxdata30rxdata15vss37rxdata63vcciorxdata33vcciorxdata1236rxdata52vssrxdata31vssrxdata035vssrxdata48rxda
74、ta32rxdata27rxdata1134rxdata53rxdata37rxdataRD1rxdata16rxdata133rxdata62rxdata47rxdataRD2rxdata26rxdata1032rxdata54rxdata38vssrxdata17vss31rxdata61rxdata46vcciorxdata25rxdata930rxdata55rxdata39rxckRDrxdata18rxdata229vssrxdata45rxvldRDrxdata24rxdata828rxdata56vssrxckn rxdata19rxdata327rxdata60rxdata4
75、4rxvld vssrxdata726rxdata57rxdata40rxckp rxdata20vss25rxdata59rxdata43rxtrkrxdata23rxdata624rxdata58rxdata41vssrxdata21rxdata423vssrxdata42vcciorxdata22rxdata522vccfwdiovccfwdiovccfwdiovccfwdiovccfwdio21vcciotxdata21vcciotxdata41txdata5820txdata5txdata22vsstxdata42vss19txdata4txdata20txckp txdata40t
76、xdata5718txdata6txdata23txtrktxdata43txdata5917vsstxdata19txckn vsstxdata5616txdata7vsstxvld txdata44txdata6015txdata3txdata18txckRD txdata39txdata5514txdata8txdata24txvldRDtxdata45vss13txdata2txdata17vcciotxdata38txdata5412txdata9txdata25vsstxdata46txdata6111vcciovcciovcciovcciovccio10txdata10txdat
77、a26txdataRD2txdata47txdata629txdata1txdata16txdataRD1txdata37txdata538txdata11txdata27txdata32txdata48vss7txdata0vsstxdata31vsstxdata526txdata12vsstxdata33vsstxdata635vsstxdata15txdata30txdata36txdata514txdata13txdata28txdata34txdata49txdataRD33txdataRD0txdata14txdata29txdata35txdata502vcciovcciovcc
78、iovcciovccio1vcciovcciovcciovcciovccioUCIe-A Bump Map Optimization16ColRecommended for 25-37um bump pitch 10Col(in spec 1.0)Recommended for 38-50um bump pitch 8Col Recommended for 51-55um bump pitch Two newly introduced bumpout configurations for maintaining optimized BW/mm2 across allowable bump pi
79、tch range Existing bumpout:10-column New:8-column,16-column Suggested usage guideline:die edgedie edgedie edgeBPMax Data Rate by SpecColumns within 388.8 shoreline25-30-44-5532824|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe
80、-A Area/Column Type Efficiency Plots Points of overlap are the optimal cross-over points between recommended 8/10/16-column bump maps At the lower bump pitch range,80%area efficiency is acceptable given overall magnitude of PHY depth is lower As bump pitch increases,90%area efficiency is desired due
81、 to the much bigger PHY depth(um)Example:10%of 1000um is greater than 20%of 400um25|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Physical Illustration x64 Bump Maps16-Col at 25 m pitch388.8 m shoreline 388 m depthdie edge10-Col at 45 m pitch 388.8 m shore
82、line 1043 m depth8-Col at 55 m pitch388.8 m shoreline 1585 m depthNote:Die bottom view looking at the micro bumps.The orientation is only for illustration purpose.The die edge shown on the left can be any of the four edges of a die.In UCIe 1.0 spec:No change26|2023 SNIA.All Rights Reserved.Property
83、of Universal Chiplet Interconnect Express(UCIe)2023UCIe 1.1:Reduced Width for Cost Optimization Some usages need x32 width native width in addition to x64(e.g.,FPGAs with lots of parallel narrower widths consistent with processing capability).One can not gang-up these x32s though(that would be x64s)
84、x64 can interoperate with a x32 by utilizing only the lower 32 lanes per module 61%area compared to x6465%area compared to x6461%area compared to x64Note:Die bottom view looking at the micro bumps.The orientation is only for illustration purpose.The die edge shown on the left can be any of the four
85、edges of a die.X32 enables lower-cost advanced packaging by allowing single layer routing in addition silicon area reduction by 40%27|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe Compliance:SetupIngredients:Reference known good package with Reference
86、 Channels,Golden Die,DUTPackage SubstrateGolden DieDUT DieGolden DiePackage SubstrateInterposer(e.g.CoWoS)DUT DieAdvanced PackageStandard Package28|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe 1.1 Enhancements:Compliance PHY level Compliance:Timing/V
87、oltage margin,BER measurement,Lane to lane skew,Even/Odd eye asymmetry,Tx EQ register based controlGolden die:all above plus ability to inject errors/cause timeouts in various phases of training D2D Adapter Compliance:DUT:Register based injection of NOP/Test Flit,Replay etc.Golden Die:Support all fo
88、rmats,ability to inject the above,error in sideband,etc Protocol Compliance:Expected to be orchestrated through an FPGA/dedicated silicon connected to the golden dieLeverage PCIe and CXL protocol compliance as defined by those specifications Streaming Protocols:Use their respective compliance29|2023
89、 Storage Developer Conference.UCIe Consortium.All Rights Reserved.UCIe Usage Models30|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023 SoC as a Package level construct Standard and/or Advanced package Homogeneous and/or heterogeneous chiplets Mix and match c
90、hiplets from multiple suppliers Across segments:Hand-held,Client,Server,Workstation,Comms,HPC,Automotive,IoT,etc UCIe PHY and D2D adapter common PCIe/CXL protocol for plug-and-play Streaming for others(similar to board level connectivity today where scale-up systems are on PCIe PHY)Similar to PCIe/C
91、XL at board levelUsage Models for UCIe:SoC at Package Level Processors:symmetric coherency protocol mapped on UCIe through FDIMemory:CXL.Mem mapped on UCIe through FDIAccelerators:PCIe/CXL mapped on UCIe through FDIModem/RF/Optical:Raw mode on UCIe 31|2023 SNIA.All Rights Reserved.Property of Univer
92、sal Chiplet Interconnect Express(UCIe)2023Example Scale-up SoC from Homogeneous Dies:Large Switch with On-Die Protocol as Streaming Over UCIe Need large radix CXL switches challenges:reticle limit,cost,etc.UCIe based Chiplets should help with scalable products 64G Gen6 x16b CXL links UCIe as d2d int
93、erconnect while this is a scale-up CXL switch,a switch vendor may prefer to have their on-die interconnect protocol be transported over UCIe rather than create a hierarchy of switches which will not work for CXL 2.0 tree-based topology Small CXL Switch(128 lanes)Medium-sized CXL Switch (256 lanes)On
94、e can construct CPUs(low,medium,large core-count CPUs)from smaller dies connected through UCIe using the same principleHere the UCIe PHY and D2D adapter will carry the packetized version of internal CPU interconnect fabric Ack:Nathan KalyanasundaramUnused x16 ports(2 per die)Large CXL switch(512 lan
95、es)32|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Example Scale-Up Package Using Streaming and Open-Plug-In Using PCIe/CXLAccelerationD2DAdapterMem controllerGPUAcceleratorsInternal(e.g.,CHI)interconnectAMBA CHIUCIeProtocolStreamingAdapterPHYTransporting
96、 the same on-chip protocol allows seamless use of architecture specific features without protocol conversionStreaming interface with additional flit formats provide link robustness using UCIe defined data-link CRC and retryPHYComputeCPUCPUCHI interconnectCPUD2DadapterMemory controllerCPUCPUCPUCPUCPU
97、CPUCPUCPUCPUPHYCHI/CXLComputeCPUCPUCHI interconnectCPUD2DAdapterMemory controllerCPUCPUCPUCPUCPUCPUCPUCPUCPUPHYD2DAdapterPHYCHI/CXLCHI/CXLUCIeProtocolStreamingAdapterPHYAny device type in this open plug-in slot with CXL(or CHI if both support it)UCIeUCIeUCIeUCIeNot drawn to scaleAck:Marvin Denman,Br
98、uce Mathewson,Francisco Socal,Durgesh Srivastava,Dong Wei(3 dies on one package)33|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023UCIe Usage:Off-Package Connectivity with Retimers(Use Case:Load-Store I/O(CXL)as the fabric across the Pod providing low-latenc
99、y and high bandwidth resource pooling/sharing as well as message passing)CXL Pooled Memory/CXL Pooled Memory/StorageStorageComputeComputeComputeComputeComputeComputeXHDD HDDXSSD SSDXCPU CPUXTORS(Compute Drawer)(w/UCIe-based SoCs)(Memory/Storage)(w/UCIe-based SoCs)Provision to extend off-package with
100、 UCIe Retimers connecting to other media(e.g.,optics)UCIe/CXL through UCIe RetimerCPUCPUMem&I/OMemMemUCIe RetimerCXL/PCIeDDRUCIeMemCPU(Interconnects at drawer level)(Optical Connection to CXL Switch on Rack)(CPU Package)(Optical connections:Intra-Rack and Pod)UCIe Retimer OpticalCXL 3.0+Switch Die(C
101、XLSwitch Package)UCIe Retimer OpticalUCIe Retimer OpticalCXL 3.0+Switch Die UCIe(Pooled/Shared Memory)CXL(Pooled Accelerator)(Another example can be multi-terabit networking switches Constructed from UCIe-based co-packaged optics and partitionable networking switch dies connected through UCIe on pac
102、kage(Switch dies connected through UCIe PHY+AdapterRunning a proprietary switch internal protocol)34|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Characteristics/KPIsData/OutcomeStandard PackageYour Key Performance Indicator goes hereAdd a few details des
103、cribing the related activities What results did you obtain from your project?Write them here.What results did you obtain from your project?Write them here.What results did you obtain from your project?Write them here.Your Key Performance Indicator goes hereYour Key Performance Indicator goes hereAdd
104、 a few details describing the related activitiesAdd a few details describing the related activitiesUCIe 1.0/1.1:Characteristics and Key MetricsData/OutcomeCHARACTERISTICSSTANDARD PACKAGEADVANCED PACKAGECOMMENTSData Rate(GT/s)4,8,12,16,24,32 Lower speeds must be supported-interop(e.g.,4,8,12 for 12G
105、device)Width(each cluster)1664Width degradation in Standard,spare lanes in AdvancedBump Pitch(um)100 13025-55Interoperate across bump pitches in each package type across nodes Channel Reach(mm)=25=2KPIs/TARGET FOR KEY METRICSSTANDARD PACKAGEADVANCED PACKAGECOMMENTSB/W Shoreline(GB/s/mm)28 224165 131
106、7Conservatively estimated:AP:45u;Standard:110u;Proportionate to data rate(4G 32G)B/W Density(GB/s/mm2)22-125188-1350Power Efficiency target(pJ/b)0.50.25Low-power entry/exit latency0.5ns=24GPower savings estimated at=85%Latency(Tx+Rx)2nsIncludes D2D Adapter and PHY(FDI to bump and back)Reliability(FI
107、T)0 FIT(Failure In Time)1FIT:#failures in a billion hours(expecting 1E-10)w/UCIe Flit ModeUCIe 1.0/1.1 delivers the best KPIs while meeting the projected needs for the next 5-6 years across the compute continuum.35|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe
108、)2023D2DSpecsC&I Test SpecTest ToolsAnd ProceduresBroad MarketManufacturing,Packagingand TestDie-to-DieIPs,VIPs,Tools,and MethodologiesChiplets&Chiplet BasedProduct AttachPointsDie-to-DieOpen Industry Standards w/compelling KPIsacross wide usagesThriving ChipletEcosystemTest criteria based on Specs(
109、Test Definitions,Pass/Fail Criteria:Electrical,Logical,Protocol,Software)Well-defined Specs(Electrical,Logical,Protocol(e.g.,PCIe/CXL)Software,Form-Factor,Management)PASSFAILPASSPredictable path to design compliance with UCIeTest H/W&S/WValidatesTest criteriaComplianceInteroperabilityIngredients for
110、 a Broad Inter-Operable Chiplet Ecosystem36|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Future Directions and Conclusions UCIe Consortium continues to evolve the UCIe Technology in a backward-compatible manner comprehending new usage models,additional co
111、st optimization,and a robust compliance mechanism UCIe is an open industry standard that establishes an open chiplet ecosystem and ubiquitous interconnect at the package level.Tremendous support across the industry with several companies announcing IP/VIP availability Evolving as the interconnect of
112、 SoCs the same way PCIe and CXL did at the board level UCIe 1.1 Specification is available to the public https:/www.uciexpress.org/specification UCIe Consortium welcomes interested companies and institutions to join the organization at the Contributor or Adopter level.6 Technical Working Groups(Elec
113、trical,Protocol,Form Factor/Compliance,Manageability/Security,Systems and Software,Automotive)and Marketing Working Group driving the technology forward Plenty of innovations happening in the consortium Join us if you have not done so!Learn more by visiting www.UCIexpress.org 37|2023 SNIA.All Rights Reserved.Property of Universal Chiplet Interconnect Express(UCIe)2023Please take a moment to rate this session.Your feedback is important to us.