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Streamlining CXL Adoption for Hyperscale Efficiency.pdf

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Streamlining CXL Adoption for Hyperscale Efficiency.pdf

1、Streamlining CXL Adoption for Hyperscale EfficiencyNilesh Shah,VP Business Development,ZeroPoint TechnologiesStreamlining CXL Adoption for Hyperscale EfficiencySustainable Scalable Computational InfrastructureSERVERChallenge4.6%3%Hyperscalers spending significant$on software based compressionCPU cyc

2、les used for compressionHyperscaler requirement:Hardware Compression is a MUST-haveDeploy New Tiers:Ordinary+Compressed DRAM memory on CXLOpportunity|Add Compressed CXL Memory TierRemoves barriers,enables diversity of Hyperscalers+Enterprise CustomersCXL ControllerBenefitSpec ComponentReduction in t

3、otal cost of ownershipStandardization,Hardware accelerated,Lossless Compressed Memory Tier Energy Efficiency,SustainabilityTransparent Hardware accelerated Compression Preserve Software InvestmentsSupport for legacy Compression Algorithms 123CXL ControllerPreserving Software Investment,without compr

4、omising performance Support for Legacy Compression AlgorithmsFuture Proof,supports Algorithm InnovationStringent Latency&Bandwidth SpecificationsRequirement:Hyperscale CXL Tiered Memory Expander SpecLegacyRoom for InnovationCompression AlgorithmsStringent RequirementsParameterSpecificationLatency Un

5、compressed Access90 to 150nsLatency Compressed Access250ns to 1usBandwidth EfficiencyRead only/Write only 80%/75%https:/www.opencompute.org/documents/hyperscale-cxl-tiered-memory-expander-for-ocp-base-specification-1-pdfCXL ControllerProposed Solution:CXL Controller with integrated Hardware Accelera

6、tionOS/HWApplicationFWCPUCompression/DecompressionCXL interfaceHostCXL.ioCXL.memMemory subsystemMediaConfigurationDynamically AdustingCompressed TierUncompressed TierCXL Type 3 Device Address SpaceCXL ControllerSolution|Portable,Integrated IPSpec compliant Plug and Play(De)Compression acceleratorCXL

7、 ControllerOCP Spec compliant Hardware Accelerated CXL memory(De)Compression+Compaction+Transparent memory management IP block2-3x transparent(de)compression major Datacenter workloadsCompression Algorithms:LZ4,ZID(proprietary)Portable:AXI4,CHI,Leading process node supportVerified 1.2Ghz,0.9mm2(at 4

8、nm Samsung)SRAM 75%of the IP solution SRAM.IP SolutionSolution|Reduce Data Center TCO 20-25%TodayWith CXL onlyWith compression onlyWith CXL&compression850780700650-20-25%CAPEX:CPUCAPEX:MemoryCAPEX:OtherOPEX:PowerOPEX:CoolingOPEX:OtherWaste:Compression taxTotal Cost of Ownership(TCO)for 40 server rac

9、k over 3y lifetime kUSDIntegrated IP Demo|QEMU+FPGAVisit the ZeroPoint Booth to see live DemoIP Solution|Performance across Datacenter workloadsSummary|Call To ActionSummary Integrated IP Solution:OCP Spec Compliant Portable across process nodes,AXI/CHI interfaceProduction ready mid 24Performance verified1stCXL Customer Solution integration announcedCall To ActionController manufacturers:Collaboratively address Hyperscale OCP requirementsISVs:Host software integration,target workloadsAdditional information(URL link)Open Discussion

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