1、ISSCC 2024Forum 5Recent Developments in High-Performance Frequency Synthesis Circuits and Systems 2024 IEEE International Solid-State Circuits ConferenceRecent Developments in High-Performance Frequency Synthesis Circuits and SystemsISSCC 2024-Forum 5:Recent Developments in High-Performance Frequenc

2、y Synthesis Circuits and Systems1 of 12Masoud BabaieDelft University of TechnologyWanghua WuSamsung Semiconductors 2024 IEEE International Solid-State Circuits ConferenceForum Organization TeamOrganizersMasoud Babaie,Delft University of Technology,Delft,The NetherlandsWanghua Wu,Samsung Semiconducto

3、r,San Jose,CACo-organizersJan Prummel,Renesas Design Netherlands,s-Hertogenbosch,The NetherlandsWei-Zen Chen,National Yang Ming Chiao Tung University,Hsinchu,TaiwanDanielle Griffith,Texas Instruments,Dallas,TXAkihide Sai,Toshiba,Kawasaki,JapanChampionsMatteo Bassi,Infineon Technologies,Villach,Austr

4、iaArun Natarajan,Oregon State University,Corvallis,OR2 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and Systems 2024 IEEE International Solid-State Circuits ConferenceFractional-N facilitates a high reference frequency and small frequency steps.Generic

5、 Block Diagram of Fractional-N Synthesizers3 of 12Time Difference MeasurementLoop FilterOutVoltage/Digital Controlled Oscillator(VCO/DCO)Multi-Modulus Divider(MMD)Edge ShifterRefDivXTALNintNdivkYkDivider ControleacckX/M=+ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis

6、Circuits and Systems 2024 IEEE International Solid-State Circuits ConferenceF5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators4 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and SystemsM.Perrott Texas InstrumentsTime Difference

7、MeasurementLoop FilterOutVCO/DCO Multi-Modulus Divider(MMD)Edge ShifterRefDivXTALNintNdivkYkDivider ControleacckX/MBAW Die-1/GMBAW Die-1/GMCvarBAW as Reference:high PLLbandwidth for best jitterBAWasVCO:lowPLLbandwidthforbestjitterbut small frequency tuningrange 2024 IEEE International Solid-State Ci

8、rcuits ConferenceF5.2:Design Techniques to Improve Phase Noise and Tuning Range of Modern RF/mmW Oscillators5 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and SystemsM.Shahmohammadi NXP SemiconductorsClass B,C,D,F ofoscillatorsTechniques to reducephase

9、 noise,such asmulti-coreoscillatorsandseries-resonanceoscillatorsTechniquestoincreaseVCOfrequencytuningrangeTime Difference MeasurementLoop FilterOutVCO/DCO Multi-Modulus Divider(MMD)Edge ShifterRefDivXTALNintNdivkYkDivider ControleacckX/M 2024 IEEE International Solid-State Circuits ConferenceF5.3:

10、Low-Power Fractional-N Digital PLL Design Techniques6 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and SystemsK.OkadaTokyo Institute of TechnologyDiscussingseverallow-powerfractional-NPLLsusingIsolated constant-slope DTCCharge-recycling DTCDuty-cycled

11、FLLSub-sampling/samplingswitching techniqueDiscussinga32kHzreference fractional-N PLLusinganoversamplingtechniqueTime to Digital Converter(TDC)Digital Loop FilterOutDCO Multi-Modulus Divider(MMD)Digital to Time Converter(DTC)RefDivXTAL(32kHz)NintNdivkYkDivider ControleacckX/M 2024 IEEE International

12、 Solid-State Circuits ConferenceF5.4:High Performance Fractional-N Digital PLLs7 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and SystemsA.RaviIntelPresentingthesystemoverviewoffractional-NAll-Digital PLLsDiscussingFrequencytuning in DCOsExplaining the

13、 pros andconsofdifferentTDCstructuresTDClinearizationtechniquesTime to Digital Converter(TDC)Digital Loop FilterOutDCO Multi-Modulus Divider(MMD)RefDivNintNdivkYkDivider ControleacckX/MEdge ShifterXTAL 2024 IEEE International Solid-State Circuits ConferenceF5.5:Design of Advanced Low-Jitter Ring Osc

14、illator-Based Injection-Locked Clock Multipliers(ICLMs)8 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and SystemsS.ParkSamsung ElectronicsDiscussingrootcausesofperformancedegradationinILCMsandtheircalibrationmethods.Introducingpower-gatingtechniques to

15、 increase operatingfrequencies with Large N.VCOSREFSOUTSINJPulse GeneratorFrequency Calibrator:Freq.Drift:Slope Modulation:Phase OffsetfDFSLOSSREF(fREF)SOUT (fOUT=N fREF)PulseGeneratorSINJSINJSVCON=4ERR(k)Ring-VCO12341234fVCOERRSREF(fREF)SOUT (fOUT=N fREF)PulseGeneratorSINJSREFSINJSVCON=4Ring-VCOfVC

16、O 2024 IEEE International Solid-State Circuits ConferenceF5.6:Prediction and Mitigation of Spurs in Fractional Synthesizers9 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and SystemsM.P.Kennedy University College DublinArchitectural spurs are introduced

17、 by:Divider ControllerNonlinearity in the loopkey sources of nonlinearity:Time difference MeasurementEdge shifterHow to mitigate nonlinearity-induced spurs?Time Difference MeasurementLoop FilterOutVCO/DCO Multi-Modulus Divider(MMD)Edge ShifterRefDivXTALNintNdivkYkDivider ControleacckX/M 2024 IEEE In

18、ternational Solid-State Circuits ConferenceF5.7:DSM Noise Suppression in AnalogFrequency Synthesizers 10 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and SystemsDavid Murphy BroadcomThere is a strong trade-off among reference,VCO and DSM noise in class

19、ic analog fractional-N PLLs,which limits PLL bandwidth.Four“calibration-free”analog PLLs that suppress DSM noise are discussedA high-reference PLLA simple DSM-overclocking PLL Two harmonic-mixing PLLsBW=2MBW=300kTime Difference MeasurementLoop FilterOutVCO Multi-Modulus Divider(MMD)RefDivXTALNintNdi

20、vkYk modulator(DSM)X/MfDSM=fref 2024 IEEE International Solid-State Circuits ConferenceF5.8:Linearization Techniques for FMCW Generation in Car Radar Applications11 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and SystemsL.GrimaldiInfineon Technologies

21、,FMCW Radar System principlesDCO nonlinearity impact on FMCW Radar operation PLL Modulation architecturesTechniques to improve linearityFrequencyTimeTX RX SLfbTchBWTime Difference MeasurementLoop FilterOutDCO Multi-Modulus Divider(MMD)Digital-to-Time Converter(DTC)RefDivXTALFCWNdivkDivider Controlea

22、cck1/fref-FMk1/KDCOFirst-order modulator+FMk 2024 IEEE International Solid-State Circuits ConferenceThank you for attending this forum!12 of 12ISSCC 2024-Forum 5:Recent Developments in High-Performance Frequency Synthesis Circuits and Systems 2024 IEEE International Solid-State Circuits ConferenceIS

23、SCC 2024 ForumsLow Jitter Frequency Generation and Synthesis Utilizing BAW ResonatorsMichael Perrott1 of 46ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits Conference2 of 46Outline Overview BAW Technology BAW App

24、lied to Phase Locked Loops(PLL)PLL architectures Jitter Cleaner,Frac-NActive Temperature CompensationBAW vs Crystal BAW Applied to Fractional Divider Frequency Generation BAW Oscillator Structures Low Power Low Noise Bondless BAW ConclusionISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Syn

25、thesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceFrequency synthesis circuit creates output frequency based on Ref frequencyFrequency multiplier(PLL):=Fractional-N PLL:has a fractional component that is non-zero Integer-N PLL:has a fractional component of zeroFr

26、equency divider:=1/Modern timing systems use a combination of the above options3 of 46Frequency SynthesisFoutNfracFrequency Synthesis CircuitRefSourceFrefISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits Conferenc

27、e4 of 46Fractional-N PLL:Key ComponentsDivideBy-NReference source and bufferBAW can be utilized as the Ref Source(for frequency generation)VCO achievable Q of on-chip LC VCO limits phase noise performanceBAW can be utilized as a VCOPhase detector,loop filter,dividerBAW can be utilized to improve PLL

28、 performancePDLoopFilterVCODeltaSigmaFrac-NPLLFoutNfracRef BufRefSourceFrefISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits Conference5 of 46DivideBy-NHigh PLL bandwidth(BW)suppresses VCO noise impact at low freq

29、uency offsetsPLL acts as a highpass filter from VCO noise to overall PLL outputKey issue:impact of non-VCO noise sources(see next slide)PDLoopFilterVCODeltaSigmaFrac-NPLLRef Buf1fPLL BWfVCO PNdBc/HzRefSourceFrefFractional-N PLL:VCO Phase NoiseFrac-NPLLfPLL PN(VCO)FoutPLL BWdBc/HzNfracISSCC 2024-Foru

30、m 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceFractional-N PLL:Non-VCO Phase Noise6 of 46DivideBy-NHigh PLL BW challenge reduces filtering of non-VCO noise sources that includeRef source and Ref bufferDelta-Sigma q

31、uantization noisePhase detector and loop filterHigh Ref frequency benefit lowers Nfracto reduce impact of non-VCO noisePDLoopFilterVCODeltaSigmaFoutRef BufFrac-NPLLfPLL BWNfracRefSourceFreffdBc/HzPLL PN(Non-VCO)PLL BWfdBc/HzRef PNfD-S PNNfracISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and S

32、ynthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceMotivation for BAW as Reference7 of 46DivideBy-NLow noise,high frequency BAW reference enables improved frac-N phase noiseDelta-Sigma runs at higher clock rate,reducing impact of quantization noiseLower divide v

33、alue reduces impact of PD,Loop Filter,and Ref Buf noiseHigher PLL bandwidth reduces impact of VCO noiseWe can more readily take advantage of high-speed circuits in advanced CMOSPDLoopFilterVCODeltaSigmaFoutRef BufFrac-NPLLfdBc/HzBAW PNFbawBAWOsc.2.1-2.5GHzNfracISSCC 2024-Forum 5.1:Low Jitter Frequen

34、cy Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceMotivation for BAW as VCO8 of 46DivideBy-NVoltage-Controlled BAW Oscillator(VCBO)enables jitter cleaning of RefAllows Low PLL BW to significantly filter non-VCO noise sources,including Ref No

35、need for high PLL BW due to excellent phase noise of VCBOKey constraint is limited frequency range of VCBOPDLoopFilterVCBODeltaSigmaFoutRef BufFrac-NPLLfdBc/HzREF PNFrefRefOsc.NfracISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Sol

36、id-State Circuits Conference9 of 46Outline Overview BAW Technology BAW Applied to Phase Locked Loops(PLL)PLL architectures Jitter Cleaner,Frac-NActive Temperature CompensationBAW vs Crystal BAW Applied to Fractional Divider Frequency Generation BAW Oscillator Structures Low Power Low Noise Bondless

37、BAW ConclusionISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceBAW Resonator Technology(Recent Examples)10 of 46E.Yen et al.,IEEE IUS,2019FBAW 2.5GHzAabaaoui et al.,IEEE MTT-S,2009FBAW 2.1GHzBAW resonat

38、or can be fabricated on a small die that is wire bonded to ASIC dieNo bias voltage required,resilient to moisture,vibration,and HeISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceBAW Resonator with Cros

39、s Section11 of 46(a)Cross section of BAW die(b)BAW die wirebondedto ASIC dieE.Yen et al.,IEEE IUS,2019Bragg reflectors confine energy without need for vacuum or hermetic packagingAllows plastic molded packaging to achieve a low-cost solutionISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Sy

40、nthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceFurther Discussion of BAW Cross Section12 of 46Bragg reflector(Acoustic Mirrors)ElectrodesPiezoelectric layerSilicon substrateBragg reflector(Acoustic Mirrors)tErnest Yen et al.,IEEE IUS,2019D.Griffith,EFTF/IFCS,

41、2023Thickness(t)of Aluminum Nitride(AlN)piezoelectric sets resonant frequencyFrequency of parallel resonance typically in range of 2GHz to 2.6GHzQ typically on the order of 1000ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-S

42、tate Circuits ConferenceBAW Model(Modified Butterworth Van-Dyke)13 of 46Bragg reflector(Acoustic Mirrors)Piezoelectric layerSilicon substrateBragg reflector(Acoustic Mirrors)tEither parallel or series resonance can be utilized to create an oscillatorParallel resonance often used for lower power cons

43、umptionLmCmRmRsC0BAWR0SeriesResonanceParallelResonanceImpedanceElectrodesB.Bahr et al.,RFIC 2022P.Vincent et al.,ISSCC 2008ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceProcess and Temp.Variation of

44、BAW Resonant Freq.14 of 46Ernest Yen et al.,IEEE IUS,2019S.Mukherjee et al.,ISSCC 2023(slides)BAW process variation of 2000ppm and temperature variation of 150ppmActive compensation required to achieve a tighter spec such as 20ppm LmCmRmRsC0BAWR0SeriesResonanceParallelResonanceImpedanceFrequency Err

45、or(PPM)Versus TemperatureProcess VariationsISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceVoltage-Controlled Frequency Adjust15 of 46Parallel resonant frequency can be adjusted with a varactorSmall tu

46、ning range,but enough for Process,Temp,Voltage(PVT)variationsLmCmRmRsC0BAWR0ImpedanceSeriesResonanceParallelResonance2Cvar2CvarVtune2 1/()20+(0+)ImpedanceP.Vincent et al.,ISSCC 2008ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Sol

47、id-State Circuits ConferenceVoltage Controlled BAW Oscillator(VCBO)16 of 46Achieve oscillator using negative resistance(1/gm)and slicer(buffer)Negative resistance typically achieved with cross coupled transistorsSlicer drives desired oscillator loadTune oscillator frequency with varactor to accommod

48、ate PVT variationsLmCmRmRsC0BAWR02Cvar2CvarVtuneFBAWCvar-1/gmBAW DieVCBOVtuneP.Vincent et al.,ISSCC 2008Slicer-1/gmISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferencePhase Noise Benefit of BAW Oscillator

49、for Slicer Noise17 of 46Slicer voltage noise can have considerable impact on oscillator jitter(phase noise)Slicer voltage noise translates to jitter according to slope of core outputIncreased slope achieved with high frequency and large voltage swing in coreHigh frequency of BAW enables reduced slic

50、er noise impact-1/gmBAW DieSlicerCoreSlicerVoltage NoiseSlopeVtuneISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits Conference18 of 46Outline Overview BAW Technology BAW Applied to Phase Locked Loops(PLL)PLL archi

51、tectures Jitter Cleaner,Frac-NActive Temperature CompensationBAW vs Crystal BAW Applied to Fractional Divider Frequency Generation BAW Oscillator Structures Low Power Low Noise Bondless BAW ConclusionISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEE

52、E International Solid-State Circuits ConferenceJitter Cleaner:Fractional PLL with VCBO19 of 46Utilize VCBO within a frac-N PLLPPM stability set by reference sourceSet low PLL BW to suppress FrefnoisePhase noise primarily set by VCBOPDLoopFilterFrefDivideBy-RCvar-1/gmBAW DieVtuneDivideBy-NDeltaSigmaN

53、fracReferenceSource(Poor Jitter)BAW Output(ExcellentJitter)Ernest Yen et al.,IEEE IFCS-ISAF,2020B.Zhang et al.,TI White Paper SNOAA34,2019DivideBy-KVCBOISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceJ

54、itter Cleaner:Measured Jitter Performance20 of 46PDLoopFilterFrefDivideBy-RCvar-1/gmBAW DieVtuneDivideBy-NDeltaSigmaNfracReferenceSource(Poor Jitter)BAW Output(ExcellentJitter)DivideBy-KVCBOExcellent jitter performance,but limited frequency rangeRMS jitter:47fs(12kHz to 20MHz)at 312.5MHz outputB.Zha

55、ng et al.,TI White Paper SN0AA34,2019ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceUtilize Locked BAW as Reference for a Frac-N PLL21 of 46Additional Frac-N allows a wide range of output frequenciesA

56、ll frequencies locked to input Frefin this approachPDLoopFilterVCODivideBy-NDeltaSigmaFrac-NPLLFoutNfracDivideBy-KFBAWCvar-1/gmBAW DieVCBOVtunePDLoopFilterDivideBy-NDeltaSigmaNfrac_bawFrefErnest Yen et al.,IEEE IFCS-ISAF,2020B.Zhang et al.,White Paper SNOAA34,2019ISSCC 2024-Forum 5.1:Low Jitter Freq

57、uency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceFrac-N PLL(LC VCO):Measured Jitter Performance22 of 46PDLoopFilterVCODivideBy-NDeltaSigmaFrac-NPLLFoutNfracDivideBy-KCvar-1/gmBAW DieVCBOVtunePDLoopFilterDivideBy-NDeltaSigmaRMS jitter:117f

58、s(12kHz to 20MHz)at 155.5MHz outputB.Zhang et al.,TI White Paper SN0AA34,2019Utilization of LC VCO degrades jitter performance relative to locked BAWRecall:RMS jitter=47fs for Locked BAWLC VCOPhase NoiseISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024

59、IEEE International Solid-State Circuits ConferenceWide Bandwidth Frac-N Example(22nm FD-SOI)23 of 46PDLoopFilterVCODivideBy-NDeltaSigmaFrac-NPLLFoutFBAWKalia et al.,JSSC 2022NfracSimple Charge Pump PLL designPower:41.4mWArea:0.307mm2PLL bandwidth:1MHzJitter:91.6fs(rms)(Fractional-N),82.7fs(rms)(Inte

60、ger-N)Integration Bandwidth:10kHz to 100MHzBAWOsc.2.5GHz20GHzISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceBAW as Reference:Active Temp.Compensation24 of 46PDLoopFilterVCODivideBy-NDeltaSigmaFrac-NPL

61、LFoutDivideBy-K-1/gmBAW DieBAWOsc.Griffith et al.,ISSCC 2020NfracPolynomialCorrectionTempSensorADCUtilize BAW oscillator as reference by compensating temperature variationFractional-N synth adjusts frequency(no need for BAW capacitive tuning)Polynomial correction determined at test using multiple te

62、mp.measurementsFBAWISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceExample Temp.Compensation Details(-40 to 125C)25 of 46PolynomialCorrectionTempSensorADCMax frequency deviation is 150ppm6-bit ADC adeq

63、uate for 10ppm2ndorder polynomial correctionEstimate with 3 Temp insertionsImproved compensation possible:Higher order polynomialHigher resolution ADCFrac-NPLLNfracGriffith et al.,ISCAS 2017BAWOsc.FoutFBAWISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 202

64、4 IEEE International Solid-State Circuits ConferenceThe Issue of BAW Aging26 of 46BAW aging estimated to be 15ppmGriffith et al.,ISCAS 2017BAWOsc.FBAWISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceExa

65、mple Overall Active Compensation Performance27 of 46Temp:10ppm3 temp trims Stress:2ppmAging:15ppmSupply:6ppm/VOverall:30ppmBAW freq:2.52GHzOsc.power:1.1mWIC process:65nmGriffith et al.,ISSCC 2020ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE Int

66、ernational Solid-State Circuits ConferenceBAW vs Crystal As Frequency Reference28 of 46BAW has the advantage of high frequency,fast startup,fewer IC pinsKey issue:higher TCF than Crystal utilize active compensation as discussed laterFBAW-1/gmBAW DiePLLVCOFvcoBAW as ReferenceXtalXTAL as ReferencePara

67、meterCrystalBAWFrequency200MHz2-2.6GHzQ10k-100k1kStartup Time1ms1usTCF,-40 to 125C 40ppm 10kHzLower BAW Q versus crystal Q impacts lower frequency offsetsBAW DiePLLVCOFPLLXtalBAWOsc.XTALOsc.selectBahr el.al.,RFIC 2022ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Re

68、sonators 2024 IEEE International Solid-State Circuits ConferenceHigh Level Summary of BAW Utilization in PLLs30 of 46BAW as VCBO:small frequency tuning range,low PLL BW for best jitterUtilize BAW to attenuate phase noise of Ref at frequency offsets PLL BWBAW as Reference:large frequency tuning range

69、,high PLL BW for best jitterUtilize BAW to suppress phase noise of VCO at frequency offsets PLL BWLeverage high frequency of BAW to reduce non-VCO noise impactFBAWCvar-1/gmBAW DieBAW as VCBOPLLFrefFBAW-1/gmBAW DiePLLVCOFvcoBAW as ReferenceRefISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and S

70、ynthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits Conference31 of 46Outline Overview BAW Technology BAW Applied to Phase Locked Loops(PLL)PLL architectures Jitter Cleaner,Frac-NActive Temperature CompensationBAW vs Crystal BAW Applied to Fractional Divider Frequency Gene

71、ration BAW Oscillator Structures Low Power Low Noise Bondless BAW ConclusionISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceFractional Output Division(FOD)with BAW32 of 46DeltaSigmaFractional Output Di

72、viderFoutDivideBy-NNPolynomialCorrectionTempSensorADCHigh frequency of BAW allows wide range of frequencies with fractional divisionDigital-to-Time Converter(DTC)utilized to reduce jitter from divider ditheringDivide-by-2 achieves even duty cycle at output for frequencies up to 200MHz Optionally inc

73、rease max frequency by 2x by utilizing two DTCs in parallelDTCS.Mukherjee et al.,ISSCC 2023 FBAWBAWOsc.2.5GHz200MHzDivideBy-2ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceExample Digital-to-Time Conv

74、erter(DTC)for FOD33 of 46Current DAC utilized for ramp-based delay controlConstant slope for ramp at transition timeAlternative DTC architectures can be consideredDTCINLCorr.DACVN1VP1VN2VP2VRSTVREFPIOUTCOMPOUTaI0(1-a)I0aI0I0VREFCOMPOUTVN1VP1VN2VP2FBAWPIOUTS.Mukherjee et al.,ISSCC 2023 ISSCC 2024-For

75、um 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceExample Active Compensation Performance(2023)34 of 46Spec:20ppmTemp:10kHz)Process:65nmBAWOscillatorCoreGriffith et al.,ISCAS 2017Griffith et al.,ISSCC 2020V0+V0-Slicer

76、AmpDetectIbiasIbiasampdesiredISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceKey Design Constraint:Low Impedance at DC37 of 46Need low DC impedance as seen by cross coupled pairAvoids latching of cross

77、 coupled pair to static stateIn this case,utilize diode connected devices(in red)BAWOscillatorCoreGriffith et al.,ISCAS 2017Griffith et al.,ISSCC 2020AmpDetectIbiasIbiasampdesiredV0+V0-ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International

78、 Solid-State Circuits ConferenceBAW Oscillator Design:Reduced Supply Voltage38 of 46Bahr et al.,RFIC 2022BAWV0+V0-SlicerOscillatorCoreAvoid stacking of bottom devices to improve headroomCore oscillator power:680uW(1.3V)Phase Noise:competitive vs crystal(offsets 10kHz)Process:65nmampdesiredIbiasIbias

79、AmpDetectISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceBAW Oscillator Design:Low Phase Noise39 of 46Transformer based structureLarge swing on BAW resonator for improved phase noiseVccBAWV0-V0+VbiasBa

80、hr et al.,RFIC 2023SlicerSlicerISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceMeasured Phase Noise(Low Phase Noise Design)40 of 46Bahr et al.,RFIC 2023Jitter=12.3fs(rms)Technology:130nm BiCMOSPower:20

81、.7mW(1.2V)Area:0.38mm2BAW mode:parallelSeries mode also possible Kalia et.al.,ASSCC 2021RMS jitter:12.3fs(12kHz to 20MHz)at 2.52GHz outputISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceBondless BAW41

82、of 46Utilize transformer coupling from IC to BAWTransformer implementation is feasible due to the high frequency of BAWBAW is attached to main CMOS die with a soft non-conductive die attach filmEnables Wafer Level Chip Scale Package(WLCSP)Reduced stress coupling between CMOS and BAW compared to stan

83、dard flip chipBahr et al.,RFIC 2021ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceBondless BAW Example42 of 46Bahr et al.,RFIC 2021Relatively simple oscillator designBAWCtuneSlicerDivideBy-4IbiasISSCC

84、 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits ConferenceBondless BAW Measured Performance43 of 46RMS jitter:43fs(12kHz to 20MHz)at 632MHz outputJitter=43fs(rms)Technology:130nm CMOSPower(Core):4mW(1.65V)Area:1.875m

85、m2(full IC)0.27mm2(core oscillator)BAW mode:parallelBahr et al.,RFIC 2021ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits Conference44 of 46Conclusion BAW enables a low cost,high frequency,low phase noise oscilla

86、torFully on-chip oscillator implementation+co-packaged BAW dieLow-cost packaging(plastic with wire bond or flip chip,WLCSP)Fast settling time and reduced pin count on ICsLow Jitter(12kHz-20MHz):Typical 50fs(rms),Best published 13fs(rms)Stability 20ppm with active compensation BAW improves performanc

87、e of various PLL structuresLow noise jitter cleaning under constraint of limited output frequency rangeLow noise,wide bandwidth frac-N phase locked loops for frequency generation We can take better advantage of high-speed circuits in advanced CMOS BAW allows frequency generation without PLLsHigh fre

88、quency of BAW allows utilization of fractional output division BAW enables new approaches for low cost,low jitter freq.generation and synthesisISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits Conference45 of 46Re

89、ferencesE.T.-T.Yen et al.,Integrated High-frequency Reference Clock Systems Utilizing Mirror-encapsulated BAW Resonators,2019 IEEE International Ultrasonics Symposium(IUS),Glasgow,UK,2019,pp.2174-2177,doi:10.1109/ULTSYM.2019.8925905.H.El Aabbaoui,J.-B.David,E.de Foucauld and P.Vincent,Ultra low phas

90、e noise 2.1 GHz Colpitts oscillators using BAW resonator,2009 IEEE MTT-S International Microwave Symposium Digest,Boston,MA,USA,2009,pp.1285-1288,doi:10.1109/MWSYM.2009.5165939.D.Griffith,BAW Advantages for Low Power IoT Applications,2023 Joint Conference of the European Frequency and Time Forum and

91、 IEEE International Frequency Control Symposium(EFTF/IFCS),Toyama,Japan,2023,pp.1-2,doi:10.1109/EFTF/IFCS57587.2023.10272054.B.Bahr,D.Griffith,A.Kiaei,T.Tsai,R.Smith and B.Haroun,Class-C BAW Oscillator Achieving a Close-in FOM of 206.5dB at 1kHz with Optimal Tuning for Narrowband Wireless Systems,20

92、22 IEEE Radio Frequency Integrated Circuits Symposium(RFIC),Denver,CO,USA,2022,pp.311-314,doi:10.1109/RFIC54546.2022.9863092.P.Vincent et al.,A 1V 220MHz-Tuning-Range 2.2GHz VCO Using a BAW Resonator,2008 IEEE International Solid-State Circuits Conference-Digest of Technical Papers,San Francisco,CA,

93、USA,2008,pp.478-629,doi:10.1109/ISSCC.2008.4523265.S.Mukherjee et al.,A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and 95fs Jitter,2023 IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,202

94、3,pp.70-72,doi:10.1109/ISSCC42615.2023.10067511.E.T.-T.Yen et al.,High-frequency Reference System Implementations Utilizing Mirror-encapsulated BAW Resonators,2020 Joint Conference of the IEEE International Frequency Control Symposium and International Symposium on Applications of Ferroelectrics(IFC

95、S-ISAF),Keystone,CO,USA,2020,pp.1-2,doi:10.1109/IFCS-ISAF41089.2020.9234834.ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2024 IEEE International Solid-State Circuits Conference46 of 46References(Continued)B.Zhang,A.Sridhar,E.T.-T.Yen,X.Lu,“TI BAW techno

96、logy enables ultra-low jitter clocks for high-speed networks”,TI White Paper SNOAA34,Feb 2019,https:/ et al.,A Sub-100 Fs RMS jitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference,in IEEE Journal of Solid-State Circuits,vol.57,no.5,pp.1372-1384,May 2022,doi:10.11

97、09/JSSC.2022.3149239.D.Griffith et al.,3.1 An Integrated BAW Oscillator with 30ppm Frequency Stability Over Temperature,Package Stress,and Aging Suitable for High-Volume Production,2020 IEEE International Solid-State Circuits Conference-(ISSCC),San Francisco,CA,USA,2020,pp.58-60,doi:10.1109/ISSCC199

98、47.2020.9062945.D.Griffith,P.T.Roine,T.Kallerud,B.Goodlin,Z.Hughes and E.T.-T.Yen,A 10ppm 40 to 125C BAW-based frequency reference system for crystal-less wireless sensor nodes,2017 IEEE International Symposium on Circuits and Systems(ISCAS),Baltimore,MD,USA,2017,pp.1-4,doi:10.1109/ISCAS.2017.805028

99、2.B.Bahr,S.Kalia,B.Haroun and S.Sankaran,Transformer-Coupled 2.5GHz BAW oscillator with 12.5fs RMS-Jitter and 1-kHz Figure-of-Merit(FOM)of 210dB,2023 IEEE Radio Frequency Integrated Circuits Symposium(RFIC),San Diego,CA,USA,2023,pp.117-120,doi:10.1109/RFIC54547.2023.10186176.S.Kalia,B.Bahr,T.Dinc,B.

100、Haroun and S.Sankaran,An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS process,2021 IEEE Asian Solid-State Circuits Conference(A-SSCC),Busan,Korea,Republic of,2021,pp.1-3,doi:10.1109/A-SSCC53895.2021.9634779.B.Bahr,A.Kiaei,M.Chowdhury,B.Cook,S.Sankaran and B.Harou

101、n,Near-Field-Coupled Bondless BAW Oscillators in WCSP Package with 46fs Jitter,2021 IEEE Radio Frequency Integrated Circuits Symposium(RFIC),Atlanta,GA,USA,2021,pp.155-158,doi:10.1109/RFIC51843.2021.9490430.ISSCC 2024-Forum 5.1:Low Jitter Frequency Generation and Synthesis Utilizing BAW Resonators 2

102、024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.1:High Performance Frequency Synthesis Utilizing BAW Resonators47 of 16Please Scan to Rate Please Scan to Rate This PaperThis PaperMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference1

103、of 79Design Techniques to Improve Phase Noise and Tuning Range of Modern RF/mmWOscillatorsMina ShahmohammadiNXP semiconductorsMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference2 of 79OutlineIntroductionTraditional Cross-coupled oscillatorsParameter definit

104、ionPhase noise and power consumption and their trade offEffect of the current source on the phase noiseSolutions to alleviate tank loadingClass-C oscillatorsCommon mode resonance at 20Extra impedance peak at 30Reducing tanks equivalent parallel resistanceMulti core oscillatorsSeries resonator Wide t

105、uning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference3 of 79Phase noiseOscillatorslowfrequencynoiseisfiltered by the PLLs loop filterIf the 1/f3corner is higher than theloop bandwidth,part o

106、f oscillator lowfrequency noise remains unfilteredPFDCharge pumpLoop filterVCONfreffLO6107108-160-140-120-100-80-60-40Frequency HzPhase noise dB Open loop OSC.Closed loop1/f31/f2Unfiltered flicker noiseMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Con

107、ference4 of 79Phase noise in generic TRXReciprocal mixing in RXfLOfRFfintfIF TX desensitizing a nearby RXfLOfIFPAfTXfTXfRXfTXfRXLNAfRXLNAfLOfRFfIFMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference5 of 79OutlineIntroductionTraditional Cross-coupled oscillat

108、orsParameter definitionPhase noise and power consumption and their trade offEffect of the current source on the phase noiseSolutions to alleviate tank loadingClass-C oscillatorsCommon mode resonance at 20Extra impedance peak at 30Reducing tanks equivalent parallel resistanceSingle core transformer b

109、ased low RttankMulti core oscillatorsSeries resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference6 of 79NMOS only cross-coupled oscillatorRobust start-upWhen M1,2enter the tr

110、iode region,loop gain is decreased and oscillation amplitude growth,saturates.VDDITM1CCLM2LD1D2RtRtVoltage efficiency:=Current efficiency:=0=2=0=VD2VD1ID1ID2VDD2VDDVoscVoltage efficiency of this structure is 1.Current efficiency of this structure is around2Mina ShahmohammadiISSCC 2024-Forum 5.2:2024

111、 IEEE International Solid-State Circuits Conference7 of 79Phase noise of the cross-coupled oscillator =10log10222 02 When M2(M1)is in triode and M1(M2)is off none of them contribute to PN.When both M2and M1are in saturation(commutating time),their noise up-converts to PN.VDDITM1CCLM2LD1D2RtRt=1+VD2V

112、D1VthVDD2VDDVoscM2in triodeM2in sat.M1in sat.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference8 of 79Figure of Merit =10log1022 02=+20log100 10log101=10log105002 Re-write the PN equation using aV,aIparameters and replacing =/0:For a fair comparison center

113、 frequency and power consumption should be normalized:Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference9 of 79Complementary cross-coupled oscillatorVDDITM1CCLM2LD1D2RtRtM3ItankM4VD2VD1ID1,4ID2,30.5VDDVDDITVoscItankIT-IT,=0.54Similar to NMOSis half the NMO

114、S=1+2Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference10 of 79NMOS vs CMOS cross-coupled oscillatorsIncreasing QtIncreasingTopology dependentIncreasing power consumptionPossiblebyincreasingthesupplyvoltage,or reducing Rt=L0Qt,byreducing L,while maintainin

115、g QtReducing circuit to phase noise up-conversion(noise factor)=10log1022 02=2NMOSCMOSGood PNLow powerIncreasing QtIncreasingTopology dependentDecreasing brings up start-up problemDecreasing supply voltageStart-up problemIncreasing Rt=L0Qtwhile maintaining Qt/Mina ShahmohammadiISSCC 2024-Forum 5.2:2

116、024 IEEE International Solid-State Circuits Conference11 of 79OutlineIntroductionTraditional Cross-coupled oscillatorsParameter definitionPhase noise and power consumption and their trade offEffect of the current source on the phase noiseSolutions to alleviate tank loadingClass-C oscillatorsCommon m

117、ode resonance at 20Extra impedance peak at 30Reducing tanks equivalent parallel resistanceMulti core oscillatorsSeries resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference12

118、 of 79Non-ideal current sourceReal ID1M1VDDCCLM2LMTVbCTTRtRtLessoscillationamplitudetoensureenough headroom for the current source,aV1.VOSCis large and pushes M1,2into triode,the drain current drops,soaI2/p.MTwill contribute to phase noise:=1+4LoweringgmTreducesMTnoisecontribution.However,MTrequires

119、 moreoverdrive voltage which limitsaV.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference13 of 79VbViM1MTCTIn1ZTInoM1VDDCCLM2RtLMTVbCTTRtTail capacitance filters out the noise of the currentsource.Theoutputimpedanceofthecurrentsourceislimited,especiallyinhi

120、gherharmonicsoftheoscillation frequency.Core transistors thermal noise,will up-convert to PNoutside the commutating region,when they operatein triode region and generating more noise.Tail Capacitance=11+(+1)VD2VD1VthVDD2VDDVoscM2in triodeM2in sat.M1in sat.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024

121、IEEE International Solid-State Circuits Conference14 of 79Whencoretransistorsareoperating in triode region,theirchannel resistance is few Ohms.Thecombinationofthislowresistanceandalargetailcapacitance,createsalowimpedancepathbetweentheinductor and ground.This will reduce the equivalenttankqualityfac

122、tor,degradingphase noise significantly.Tail CapacitanceM1VDDCCLM2LMTVbCTTRtRtDischarge path20406080014000.0050.010.0150.020.0250.0320406080023456Class-F transient waveform3210-1VG1VD1M1 drain source conductance(mS)020225155Loaded quality f

123、actor(QL)021510502531Loaded tank noise normalized to inherent tank noise1234 i2n,tank =i2tank4kTGpQL=Lp(Gp+GDS)20406080014000.0050.010.0150.020.0250.0320406080023456Class-F transient waveform3210-1VG1VD1M1 drain source conductance(mS)02022

124、5155Loaded quality factor(QL)021510502531Loaded tank noise normalized to inherent tank noise1234 i2n,tank =i2tank4kTGpQL=Lp(Gp+GDS)QL=1/L(Gt+GDS)Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference15 of 79OutlineIntroductionTraditional Cross-coupled oscillat

125、orsParameter definitionPhase noise and power consumption and their trade offEffect of the current source on the phase noiseSolutions to alleviate tank loadingClass-C oscillatorsCommon mode resonance at 20Extra impedance peak at 30Reducing tanks equivalent parallel resistanceMulti core oscillatorsSer

126、ies resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference16 of 79Keepingthecoretransistorsalways in saturation by reducingoscillation amplitude.CTcan be large and filter bias

127、transistor noise.SmallaVlimits the phase noise.Class-C oscillatorM1VDDCCLM2RtLMTVbCTTRt2VDDVDDVosc +D1D222Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference17 of 79M1VDDCCLM2LMTVbCTVbiasDecouples gate and drain dc voltage.LowenoughVbiasensuresM1,2saturatio

128、n operation.Largeenoughtailcapacitanceforclass-Coperationwithtallandnarrow current,improvesaI1The optimum Vbiasin start-up andsteady state are different.Dynamicbiasing improves the performance.High FoM,but its low VOSClimits thephase noise performance.Class-C oscillator2VDDVDDVoscVbiasD1G1+2212 1IT3

129、IT02p pClass-CCross-coupledMazzanti-08Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference18 of 79Vbiasat start-up and steady state shouldnt be necessarily similar.Sense the VCMvoltage,adjusting Vbiasin a feedback loop.RBWis shorted at start-up for a fast se

130、ttling.At steady state,the M3isdisabled to create a narrow bandwidth feedback to filter feedback noise.Dynamic bias Class-C oscillatorMTVbCTCBWRBWM3Vref+-M1VDDCCLM2LVbiasC1C1VCMFanori-13Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference19 of 79OutlineIntro

131、ductionTraditional Cross-coupled oscillatorsParameter definitionPhase noise and power consumption and their trade offEffect of the current source on the phase noiseSolutions to alleviate tank loadingClass-C oscillatorsCommon mode resonance at 20Extra impedance peak at 30Reducing tanks equivalent par

132、allel resistanceMulti core oscillatorsSeries resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference20 of 79Reducing circuit to phase noise up-conversionIf VOSCis flat when M1,

133、2are in triode region,theexpected ISF is almostzero.ThetankandMOStransistors noises cantup-convert to PN.What tank can offer suchan oscillation voltage?Tank impedanceDrain currentTank Voltageff02f03f0ff02f03f0fVH1f02f03f0IH1IH2IH3/200ff02f03f0Common modeDifferential modeVH2ID1ID2tM1VDDMTVbCTTin2=4kT

134、gdsin2=4kT/RtM2Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference21 of 79Sinusoidal oscillation waveformVDD02VDDID1ID2V1V2tI0IH1IH2IH3IH4/20/2ID1CommonmodeDifferentialmode0IH1IH2IH3IH4/2/2f02.f03.f04.f0 I0ID2Tank current is harmonically rich.The resonators

135、 impedance,filters higher orderharmonics.How to create an oscillation waveform thatcontains higher harmonics?ID,H1ID,H2ID,H3f02f03f0ff02f03f0fff02f03f0Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference22 of 79Clipped oscillation waveform with 2ndharmonicIf

136、thetankhasaCMresonanceat2f0,a2ndharmonic in the oscillationwaveform appears,whichresults in a clipped Osc.waveformHowtorealizesuchatank?Tank impedanceDrain currentCMDM3f02f0f0ID,H10ID,H30ID,H2p/2f3f02f0f0f3f02f0f0fTank Voltage3f02f0f0fID1ID2Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE Internatio

137、nal Solid-State Circuits Conference23 of 79A resonator at 2w0is inserted between the core transistors and MTto create a high impedance path.MTnoise is filtered by a relatively large capacitor.Excellent PN and FoM(196dBc/Hz),but with large area penalty.Needs tuning for a wide band operation.Noise fil

138、tering techniqueVDDM1CCLM2LMTC1VbLTCTRtRtHegazi-01Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference24 of 79The common mode of the main tank affects the effectiveness of the filteringtechnique.In fact,the common mode of the entire circuit should resonate a

139、t2w0.Implicit Common mode resonanceCpM1CDMCDMLM2LLTCTkmCCMCCMVDDCpDifferential mode(DM)impedanceLTCT0.5CDMCpLkmCpCCMZDM=1+|1|1|1wDMMurphy-17Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference25 of 79wCMThe common mode of the main tank affects the effectiven

140、ess of the filtering technique.In fact,the common mode of the entire circuit should resonate at 2w0.Implicit Common mode resonanceCpM1CDMCDMLM2LLTCTkmCCMCCMVDDCpCommon mode(CM)impedance=(1|1+2|2)|1LTCT0.5CDMCpLkmCpCCMZCMMurphy-17Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-St

141、ate Circuits Conference26 of 79It is possible to remove the tail resonance and still getwCM=2wDM.Implicit Common mode resonanceCM=1|1|10.5CDMCpLkmCpCCMZCMZDM0.5CDMCpLkmCpCCMDM=1+|1|1|1w02w0=3 51+Murphy-17Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference27

142、 of 79Implicit Common mode resonanceMurphy-17The CM cannot resonateat 20,if k0.6.Very small k results inimpractically small CCM.k=0.3 is chosen.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference28 of 79Implicit Common mode:method-2Twoturninductorshowsdiffe

143、rentDMandCMinductances.In DM,currents in both turns have the same direction,thus additive magnetic flux.In CM,currents have opposite direction and cancel eachother magnetic flux.Shahmohammadi-.511.5Input inductance(nH)435Frequency(GHz)DMCMLDM/LCMInductance ratio is controlled through lith

144、ography and quite precise,with proper spacing:Magnetic flux cancellation 4Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference29 of 79Tanks capacitor bank should be singleended for CM=2DM.Degrades Qtfor the same tuning range.LTaffects thewDM/wCMand should be

145、 modeled properly.Implicit Common mode:method-2Shahmohammadi-400Zin Magnitude()Frequency(GHz)DM fminDM fmaxCM fmaxCM fminCcCcZinLpLpLTMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference30 of 79Partiallyflatoscillationvoltage,negligible

146、 ISF.Flicker noise corner is alsolow in this design.Implicit Common mode:method-2M2M1VDDCCLLD1D2Lpar00.511.50t(psec)Voltage waveforms(V)-1012 Shahmohammadi-16Oscillation frequency(GHz)3.53.73.94.14.34.57080901001/f3 corner(kHz)Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International

147、 Solid-State Circuits Conference31 of 79The flicker noise of M1,2in a cross-coupled oscillator is a cyclo-stationary process:,0is a stationary process and(0)is a deterministicperiodic function,nominalized to have a maximum of 1.From the ISF theory we know that flicker noise does notup-convert to pha

148、se noise if the dc level of the effectiveISF is zero.Flicker noise up-conversion,1/2=1 1,202,1/2M2M1VDDCCLL1,1/20=(0)(0),1/=,0 (0)0=(0),Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference32 of 79Flicker noise up-conversionM2M1VDDCCLL2-101 eff M2M1VDDCCLL-10

149、12 eff 00.511.50t(psec)Voltage waveforms(V)000.511.5 waveforms(V)t(psec)More symmetric waveformsLess dc value of Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference33 of 79Lim-18QCMeffect on phase noiseIn both implicit CM methods;the C

150、M resonance Q is low.HigherQCMextendstheflattened part of the oscillationvoltage,andconsequentlyreducescircuittoPNup-conversion.Low QCMHigh QCMNegligible noise up-conversion=+Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference34 of 79Inverse class-FLim-18Lo

151、werzfacilitate lower PDC,buthigherzoffers lower PN.=Transformerbasedtankhastwo resonances.Creates two high-Q impedanceatw0and 2w0.LSCSCPLPVGVDIDVDDZin=0.38Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference35 of 79Inverse class-FThecentertap ofthetwo coils

152、are shorted toprovideself-biasingatVDD/2,given that MPandMNare sized such thatgm,p=gm,n.The loop gain fulfills thephase condition only atthe low frequency.The ISF is negligible formoretimeduringoscillation period.EffectiveISFhasanegligible dc value.Lim-18LSCSCPLPVDDVGPVGNVDPVDNMina ShahmohammadiISSC

153、C 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference36 of 79Inverse class-FThecentertap ofthetwo coils are shorted toprovideself-biasingatVDD/2,given that MPandMNare sized such thatgm,p=gm,n.The loop gain fulfills thephase condition only atthe low frequency.The ISF is negligible

154、formoretimeduringoscillation period.EffectiveISFhasanegligible dc value.Lim-18LSCSCPLPVDDVGPVGNVDPVDNMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference37 of 79Automatic CM resonance calibrationGong-20IfwCMdeviates from 2w0,phase noisewilldegrade.Optimumpoi

155、ntthenshould be found manually.Oscillationvoltage2ndharmoniccomponent(AH2)ismaximumwhenwCM=2w0.The goal of the calibration is to find bCDand bCCthat maximizes AH2.Starts with bCC=0 and bCDis the code to reach the desired w0.VDACset at maximum,and DCP=1.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEE

156、E International Solid-State Circuits Conference38 of 79Automatic CM resonance calibrationGong-20Manually tuned the oscillator to find thebest and worst PN profile.Then let the automatic calibration work.Very close to the best noise profile andup to 10.7dB improvement in PN overthe tuning rangeMina S

157、hahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference39 of 79OutlineIntroductionTraditional Cross-coupled oscillatorsParameter definitionPhase noise and power consumption and their trade offEffect of the current source on the phase noiseSolutions to alleviate tank

158、loadingClass-C oscillatorsCommon mode resonance at 20Extra impedance peak at 30Reducing tanks equivalent parallel resistanceMulti core oscillatorsSeries resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International

159、 Solid-State Circuits Conference40 of 79Clipped oscillation waveform with the 3rdharmonicIfthetankhasa2ndresonanceat3f0,a3rdharmonic in the oscillationwaveformappears,whichresults in a pseudo square-waveformHow to realize such a tank?Tank impedanceDrain currentTank Voltage3f02f0f0ID,H10ID,H30ID,H2p/

160、2f3f02f0f0fID1ID23f02f0f0fMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference41 of 79A transformer-based tank offers two resonance frequencies.km0.8 for possibility of w2=3w0.Class-F3oscillator1=1+=CPLPLSCSVoutVinZinBabaie-13LargerLS/LPmeanshigherinter-wind

161、ingvoltage gainSharpertransitionatzero-crossingsandlarger oscillation amplitude at the secondarywinding,thus better PN.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference42 of 79Class-F3oscillatorCPCPM1VDDLPM2LPLSLSVBCsCskmMTVb1CTD1D2G1G2This structure ensu

162、res start-up possibility only at the first resonant frequency.Thick oxide devices are needed due to high voltage gain of the tank to ensure reliability.Babaie-13FoM(dBc/Hz)Phase Noise 3MHz(dBc/Hz)192190-141-14333.23.43.63.8-142191193Frequency(GHz)(After on chip/2)Class-B/CClass-F-1-0.500.5102M1,2-1-

163、0.500.5102Class-FClass-B/Ctank-10123VG1VD1V-F=0.802Waveforms(V)Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference43 of 79Implicit Common mode in class-F3Shahmohammadi-161:2 turn transformer shows different DM and CM inductances.In DM:the induced currents a

164、t the secondary side circulate in the same direction leadingto a strong,km,d.In CM:the induced currents cancel each other,resulting in a weak km,c.The secondary winding cannot be seen by the CM signals.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference44 o

165、f 79Implicit Common mode in class-F3Shahmohammadi-16,1=1+To realize a CM resonance,capacitors at theprimary side should be SE.LSCS=3LPCPfor CM=2DM,1and km,d=0.67for DM,2=3DM,1.HighCMimpedanceisbeneficialforPNperformance.,1=1CsCsZinVDDCpCpVBkmLpLpLsLsLTFrequency(GHz)0500200300400DM fminDM

166、fmaxCM fmaxCM fmin24681022.22.42.62.833.2Frequency(GHz)f1,DM/f0,DMfCM/f0,DMMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference45 of 79Wideband harmonic shaping oscillatorGuo-21Extra tuning is needed for CM and 2ndDM resonance.Exploits a muti LC tank to real

167、ize wideband CM and DM resonances at 2w0and 3w0and eliminate tuning.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference46 of 79Guo-21Addedasmallcoilheadresonator to make a higher-orderwidebandCMresonancetogether with the SE CdandLd,cm.Apairofcomplexzerosbet

168、ween two adjacent pairs ofcomplexpolesat2w0arerealized.Higher kmfor smaller CM phaseripple.Mistune the 2ndDM resonancefrom 3w0with Cdd.Wideband harmonic shaping oscillatorMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference47 of 79VTis s virtual AC ground fo

169、r the DM excitation;thus,HRhas no impact on the DM resonance and DM and CMresonances can be optimized independently.Frequency tuning only at the gate side with Cgcapacitor bank.Negligible ISF when VDPis flat.Wideband harmonic shaping oscillatorGuo-21Cdkm1VDDC1L1L2km2CddCddCgCgCdM1DPGNLdLgLdLgVGBVTMi

170、na ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference48 of 79OutlineIntroductionTraditional Cross-coupled oscillatorsParameter definitionPhase noise and power consumption and their trade offEffect of the current source on the phase noiseSolutions to alleviate t

171、ank loadingClass-C oscillatorsCommon mode resonance at 20Extra impedance peak at 30Reducing tanks equivalent parallel resistanceMulti core oscillatorsSeries resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE Internati

172、onal Solid-State Circuits Conference49 of 79Reducing tanks equivalent parallel resistanceReducinginductanceofacoil,reduces Rtwhile maintaining Q.Smallinnerdiametersincreasecouplingbetweenthetracesandreduce the coils inductance per unitlength.AtsomepointinterconnectlosscontributiontotheQbecomesvisibl

173、e.=10log10222 02Murphy-18Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference50 of 79Propose a tank to reduce Rt(Rin)with two step up transformersthat are connected back-to-back.Rinideally reduces by a factor of1+n2,potentiallybetterthancoupled oscillators.I

174、ncreasingn,willeventuallyresult in lower Q.n=2 is chosen.Single core low RtBabaie-15Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference51 of 79Propose a tank to reduce Rt(Rin)with two step up transformersthat are connected back-to-back.Rinideally reduces by

175、 a factor of1+n2,potentiallybetterthancoupled oscillators.Increasingn,willeventuallyresult in lower Q.n=2 is chosen.Single core low RtBabaie-15VDDC1C1LPLPDADBC2C2LSLS1:2LPLPLSLS1:2VBC3C3CTVb1GAIMAGBIMBMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference52 of

176、 79Realizing implicit CMBabaie-15111+2 1+1+22+3411+2111=2Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference53 of 79OutlineIntroductionTraditional Cross-coupled oscillatorsParameter definitionPhase noise and power consumption trade offEffect of the current

177、source on the phase noiseSolutions to alleviate tank loadingClass-C oscillatorsCM oscillation at 20Reduce circuit to phase noise up-conversionReducing tanks equivalent parallel resistanceMulti core oscillatorsSeries resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusio

178、nMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference54 of 79Multi-core oscillatorsCouples N oscillators together and benefit from theoretically 10log10 phasenoise improvement.Area is N times higher.Mismatch between the cores degrades PN.Unwanted multi-mode

179、oscillation can happen.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference55 of 79Dual-core oscillatorOscillators are coupled by shorting their outputs via thick oxide NMOS switches(ron=10W)Wu-21Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International

180、 Solid-State Circuits Conference56 of 7927-GHz Quad-core oscillatorMurphy-18Circular geometry topologyfour-slab inductors connected in acircleviafourfullycomplementary oscillator coresLatching and mode ambiguity areavoided by connecting the virtualgrounds of each slab inductor bymeans of high-resist

181、ance tracesMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference57 of 79OutlineIntroductionTraditional Cross-coupled oscillatorsParameter definitionPhase noise and power consumption trade offEffect of the current source on the phase noiseSolutions to alleviat

182、e tank loadingClass-C oscillatorsCM oscillation at 20Reduce circuit to phase noise up-conversionReducing tanks equivalent parallel resistanceMulti core oscillatorsSeries resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 I

183、EEE International Solid-State Circuits Conference58 of 79Series LC tankFranceschin-22=0=0/=10log102Breaks the limitation of lowering equivalent resistance of the parallel tanks byexploiting a series resonatorRe-writing phase noise equation with active power:=10log1022 02=22=220=22=220=2Mina Shahmoha

184、mmadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference59 of 79Series LC tankFranceschin-22Negativeconductanceatthequiescent pointCurrent saturation at large signalStart-up condition:1Negativeresistanceatthequiescent pointVoltage saturation at large signalStart-up condition

185、:Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference60 of 79Series LC tankFranceschin-22Start-up condition:RRsMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference61 of 79Series LC tank-Ultra low phase noise designFr

186、anceschin-22dc current is sustained by two tail inductors.dcbasevoltageofQ1,2isshiftdowncompared to collectors by CCand applying VB1with the choke inductors of LB1.Lpresonates with parasitic capacitance.LPis a small low Q inductor to feed supplyvoltagetoQ1,2andcreatetherequiredresistance.Mina Shahmo

187、hammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference62 of 79Series LC tank-Ultra low phase noise designFranceschin-229%tuning rangeQ=20Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference63 of 79OutlineIntroductionTraditional C

188、ross-coupled oscillatorsParameter definitionPhase noise and power consumption trade offEffect of the current source on the phase noiseSolutions to alleviate tank loadingClass-C oscillatorsCM oscillation at 20Reduce circuit to phase noise up-conversionReducing tanks equivalent parallel resistanceMult

189、i core oscillatorsSeries resonator Wide tuning range oscillatorsChallengesMode-switching oscillatorsConclusionMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference64 of 79Tuning range extension limitationsMulti standard applications call for wide tuning range

190、 oscillators with phase noise comparable to usual oscillatorsThere is a trade off between Q of the tank and the tuning range of an oscillatorDiscrete tuningContinuous tuningCparCparCvaraWLCpara WRvara L/W2CparCvarTrade off between minimizing Rvar(Qvar)and CparRbCronCRCCparCCRRCparCQon=0.5ronCw0Con=0

191、.5CQoff=RCparw0Coff=0.5C.Cpar/(C+Cpar)Trade off between minimizing ron(Qon)and CparMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference65 of 79Tuning range extension limitationsMulti-core oscillators seems to bethe obvious solution in expenseof Large area.Pu

192、tting one coil underneath theother:8-shapedinducesverylowmagnetic field on another coilif placed along the latters axisof symmetry.Rotatedthesmalleroneby90.Area is still considerable.Needshighfrequencysourceselecting multiplexers.Fanori-16Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE Internationa

193、l Solid-State Circuits Conference66 of 79Resonant mode switching(dual mode)=1+=1 +Involves two or more resonators connected through a network of switches,Gm-cells,or a combination for mode selectionNo current flows in the switches for both modes,thus no Q(PN)degradation.Li-12CcCMLCLCcZinCL+MCL+MCcCc

194、C+CcL-MC+CcL-MMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference67 of 79Resonant mode switching(dual mode)Li-12Low kmLarge area(0.29mm2)77%TR5dB FoM variationMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference68 o

195、f 79Resonant mode switching(series resonator)The resonator has two inductors of inductance,L,each connected in series and has two modes of operation.=1=12(2+)Like two coupled oscillators 2LCLBCDCDL-Gm,HB-Gm,HBENHBENHB-Gm,LBENLBkHB(even)LB(odd)P1P2P3P4LCD-Gm,HBkCDL-Gm,HBP2P3P4P1-+2L(1-k)CLB+CD/2-Gm,L

196、BP4P1-+Agrawal-17Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference69 of 79Resonant mode switching(series resonator)The inductor center tap point is mode dependent.The supply voltage for Gmcells are provided via PMOS switches to correspondent center tap po

197、intAgrawal-170.126mm24dB FoM variation 75%tuning rangeMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference70 of 79Dual-core triple-mode-switching oscillatorIt is still challenging for octave tuning dual-mode oscillatorsto offer competitive FoM.The outer and

198、inner inductors are realized between P1-P2and P3-P4ports with a self-inductance of 2L1+2L3and2L2+2L3By DM or CM excitation of the ports of the inductorsthrough-GM1-4and mode-selection switches three differentequivalent inductances and capacitances are realized.Offers a solution to reduce the oscilla

199、tors area.Gong-22Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference71 of 79Dual-core triple-mode-switching oscillatorGong-221=12 2+23+12 222=12 2 12 22(+)3=11+2 212+22mode1mode2mode3Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State

200、 Circuits Conference72 of 79Dual-core triple-mode-switching oscillator3dB FoM variationSmall area 0.049mm2Gong-2280.6%tuning rangeFoMT=FoM+20log10(TR/10)Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference73 of 79Quad-core quad-mode switching oscillatorTwore

201、sonanttankscoupledelectrically(via coupling capacitor)andmagnetically(coupledtransformers).Amode-switch array is used toselect the coupling phases of theE-and M-coupling(i.e.,even modeor odd mode)and to achieve thequad-mode mode switching.Shu-20Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE Intern

202、ational Solid-State Circuits Conference74 of 79Quad-core quad-mode switching oscillatorShu-202=1+3=1 (+)4=1 (+)1=1+(+)Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference75 of 79Quad-core quad-mode switching oscillatorShu-200.08mm273%tuning range3dB FoM vari

203、ation73.2%tuning rangeMina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference76 of 79ConclusionTraditional cross-coupled oscillator,its phase noise and power consumptiontrade off is discussed.The effect of a non-ideal current source on the phase noise degradati

204、on isexplained.Some topologies and design techniques to mitigate circuit to phase noiseup-conversion when core transistors are in triode region are reviewed.The limitations of reducing tank equivalent parallel resistance and multi-core oscillators are discussed and showed how employing a series reso

205、natorenables us to design ultra low phase noise oscillators.The wide tuning range oscillator design challenges are discussed andreviewed how mode-switching oscillators can improve on tuning range.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference77 of 79Ac

206、knowledgement Thanks to my colleagues at NXP Semiconductors for thehelpful discussions.Thanks to D.Griffith,J.Prummel,W.Wu,and M.Babaie fortheir valuable feedbacks on the presentation.Thank you for your attention!Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Con

207、ference78 of 79ReferencesB.Razavi,“A Study of Phase Noise in CMOS Oscillators,”JSSC,March.1996,pp.331-343.A.Hajimiri and T.H.Lee,“A General Theory of Phase Noise in Electrical Oscillators,”JSSC,Feb.1998,pp.179-194.M.Garampazzi et al.,“An Intuitive Analysis of Phase Noise Fundamental Limits Suitable

208、for Benchmarking LC Oscillators,”JSSC,Mar.2014,pp.635-645.A.Mazzanti and P.Andreani,“Class-C harmonic CMOS VCOs,with a general result on phase noise,”ISSCC 2008,paper 26.2Expanded version in JSSC,Dec.2008,pp.2716-2729.L.Fanori and P.Andreani,“Highly efficient class-C CMOS VCOs,including a comparison

209、 with class-B VCOs,”JSSC,Jul.2013,pp.1730-1740.E.Hegazi et al.,“A Filtering Technique to Lower LC Oscillator Phase Noise,”JSSC,Dec.2001,pp.1921-1930.D.Murphy et al.,“Implicit Common-Mode Resonance in LC Oscillators,”ISSCC 2016,paper 2.5.Expanded version in JSSC,Mar.2017,pp.812-821.M.Shahmohammadi et

210、 al.,“A 1/f Noise Up-conversion Reduction Technique for Voltage-Biased RF CMOS Oscillators,”ISSCC 2016,paper 2.6.Expanded version in JSSC,Nov.2016,pp.2610-2624.C.C.Lim et al.,“An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances,”ISSCC 2018,paper 23.

211、5.Expanded version in JSSC,Dec.2018,pp.3528-3539.J.Gong et et al.,“Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications,”ISSCC 2020,paper 19.3.Expanded version in JSSC,Dec 2022,pp.4810-4822.M.Babaie and R.B.Staszewski,“A Class-F CMOS Oscillator,

212、”JSSC,Dec.2013,pp.3120-3133.H.Guo et al.,“A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz peak FoM and 90-to-180kHz 1/f3PN Corner Without Harmonic Tuning,”ISSCC 2021,paper 20.1.D.Murphy and H.Darabi,“A 27-GHz Quad-Core CMOS Oscillator With No Mode Ambiguity,”JSSC,Nov.18,pp.3208-

213、3216.M.Babaie and R.B.Staszewski,“An Ultra-Low Phase Noise Class-F2CMOS Oscillator with 191 dBc/Hz FOM and Long TermReliability,”JSSC,Mar.2015,pp.679-692.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference79 of 79ReferencesW.Wu et al.,“A 14-nm Ultra-Low Jit

214、ter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO,”ISSCC 2021,paper 32.2.Expanded version in JSSC,Dec.2021,pp.3756-3766.Franceschin et al.,“Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance,”ISSCC 2022,paper 9.1.Expanded version in J

215、SSC,Dec.2022,pp.3514-3526.A.Fanori et al.,“A 2.4-to-5.3GHz Dual-Core CMOS VCO with Concentric 8-Shaped Coils,”ISSCC 2016,paper 21.5.G.Li et al.,“A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching,”JSSC,Jun.2012,pp.1295-1308.A.Agrawal and A.Natarajan,“Series Resonator Mod

216、e Switching for Area-Efficient Octave Tuning-Range CMOS LC Oscillators,”TMTT,May 2017,pp.1569-1579.J.Gong et al.,“A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoMAin 22nm FinFET,”ISSCC 2022,paper 9.2.Y.Shu et al.,“A 18.6-to-40.1GHz 201.7dBc/Hz FoMTMulti-Core Oscillator Using E

217、-M Mixed-Coupling Resonance Boosting,”ISSCC2020,paper 17.4.Mina ShahmohammadiISSCC 2024-Forum 5.2:2024 IEEE International Solid-State Circuits Conference80 of 79Please Scan to Rate Please Scan to Rate This PaperThis PaperKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Tec

218、hniques1 of 81 2024 IEEE International Solid-State Circuits ConferenceLow-Power Fractional-N Digital PLL Design TechniquesKenichi OkadaTokyo Institute of TechnologyKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques2 of 81 2024 IEEE International Solid-State Circui

219、ts Conference Introduction DTC DCO DTC-based ADPLL Sampling/Subsampling-switching ADPLL Oversampling PLL ConclusionOutlinesKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques3 of 81 2024 IEEE International Solid-State Circuits ConferencePLL RequirementsApplication-

220、dependent requirements for PLLs Output frequency range Reference frequency Integer-N/Fractional-N Phase noise(integrated phase noise,spurs)Clock jitter(random,deterministic)Power consumption Settling time,calibration time PVT Supply sensitivity etcKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fraction

221、al-N Digital PLL Design Techniques4 of 81 2024 IEEE International Solid-State Circuits ConferenceState-of-the-Art BLE TRX w/ADPLL IntegratedJitter and Spur requirements limit lowering PDCof ADPLL.Power Consumption in Low-Power WirelessKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital

222、PLL Design Techniques5 of 81 2024 IEEE International Solid-State Circuits ConferencePhase Noise of PLLoffset frequency Phase noiseVCO/DCOPLL Phase noiseCP/TDC=()spurspur=()Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques6 of 81 2024 IEEE International Solid-Stat

223、e Circuits ConferenceTarget of This TalkLow-Power Fractional-N PLL(1mW with good FoM)Analog vs Digital Integer-N vs fractional-N(*integer-N is much easier)Ring vs LC Full-range TDC vs DTC-assisted TDC Sampling vs Sub-sampling(for low-power not for low-noise)and Over-sampling PLL for lower reference

224、clock Fractional spur mitigationKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques7 of 81 2024 IEEE International Solid-State Circuits ConferenceInteger-N or Fractional-NTDCDLFMMDrefTDCDLFMMDDTCrefInteger-N PLLFractional-N PLLNarrow range Much easier to design Inj

225、ection-locked PLL,MDLL can be used FoM TDCOJitter2 DRPdc DRFine resolution&High linearity DTC-assisted ADPLL Narrow-range TDC can be used.e.g.500ps-range DTC with 50ps TDC instead of 500ps-range TDC ,Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques9 of 81 2024 I

226、EEE International Solid-State Circuits ConferenceTheoretical Limit of Integer-N PLL=()when,=,=()+=()=,.=+=()=,if is smaller than optimal Injection-locked PLLType-I/II PLLH.Zhang,et al.,0.2mW 70fs rms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving-2

227、70dB FoM and-66dBc Ref Spur,VLSI Circuits 2019.Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques10 of 81 2024 IEEE International Solid-State Circuits ConferenceTheoretical Limit of Integer-N PLLType-I PLLType-II PLLInjection-Locked PLL(x)0.5x0.1x0.4xFoM-283dB-276

228、dB-279dB=/,=,No in-band CP/TDC noise,no flickerRef.doubler can contribute an additional 3dB improvement by doubled=(),H.Zhang,et al.,0.2mW 70fs rms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving-270dB FoM and-66dBc Ref Spur,VLSI Circuits 2019.Kenic

229、hi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques11 of 81 2024 IEEE International Solid-State Circuits ConferenceInjection-locked PLL with FoM=-271dB Class-D VCOPulse-generatorFreq.trackingloop and FLLSPIREFDZPFD/NRCPulse Gen.DSSPDCPLFCPLFREFINJBWSSPD:417ps/cycleKenic

230、hi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques27 of 81 2024 IEEE International Solid-State Circuits Conference Introduction DTC Isolated Constant-Slope DTC Truncated Constant-Slope DTC DCO DTC-based ADPLL Sampling/Subsampling-switching ADPLL Oversampling PLL Conclu

231、sionOutlinesKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques28 of 81 2024 IEEE International Solid-State Circuits ConferenceVTH Reset C to VSS using S3 S2 turns on to charge C to VDACJ.Z.Ru，JSSC 2015Conventional Constant-Slope DTCKenichi OkadaISSCC 2024-Forum 5.

232、3:Low-Power Fractional-N Digital PLL Design Techniques29 of 81 2024 IEEE International Solid-State Circuits ConferenceD2D1VTHD3 D1 and D3 waste 58%power from current source Leakage power from inverter(VDACclose to VTH)Conventional Constant-Slope DTCKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractio

233、nal-N Digital PLL Design Techniques30 of 81 2024 IEEE International Solid-State Circuits Conference Introducing a feedback loop from DTC output to its inputConventional DTC:Proposed DTC:TruncationLogicTruncated Constant-Slope DTCKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL De

234、sign Techniques31 of 81 2024 IEEE International Solid-State Circuits ConferenceVTHGatingLogicTruncationLogicDischarge Step S2 turns on to discharge C to VDAC(Charge recycling)S3 prevents large leakage current from the inverterKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Desig

235、n Techniques32 of 81 2024 IEEE International Solid-State Circuits ConferenceCompare StepVTHGatingLogicTruncationLogic Good linearity thanks to constant-slope delay generationKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques33 of 81 2024 IEEE International Solid-S

236、tate Circuits ConferenceTruncation StepVTHGatingLogicTruncationLogic S1 is cut off by non-reset logic to save current source power The constant slope is 100%used for delay generationKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques34 of 81 2024 IEEE International

237、 Solid-State Circuits ConferenceComparison of Operation9-bit current sourcefor gain cal.Truncated DTC Improved efficiency for current source(58%improved)Peak INL of 300fs with 1.9ps/LSB resolution Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques35 of 81 2024 IEE

238、E International Solid-State Circuits ConferenceDTC ComparisonH.LiuISSCC19H.LiuISSCC18J.Z.RuJSSC14PavlovicISSCC11D.TascaJSSC11N.MarkulicESSCIRC14ArchitectureTruncatedconstant slopeIsolatedconstant slopeConstant slopeVariable slopeVariable slopeVariable slopeTechnology65nm65nm65nm65nm65nm28nmDelay ran

239、ge490ps593ps189ps186ps338ps563psResolution1.9ps0.58ps0.185ps4.7ps0.33ps0.55ps#bit8(+9 gain cal)1010 417ps/cycleKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques36 of 81 2024 IEEE International Solid-State Circuits ConferenceOther Techniques for Mitigating DTC INL

240、Digital Pre-Distortion(DPD):Very effective in spur reduction Different DPD schemes should be selected based on the characteristicsof spur source Can work in background,but usually requires long convergence timeDither:A brute-force way Scramble spur power into random noise(jitter still remains)Dither

241、ing itself can sometimes add more noise,needs to be canceledS.Levantino,JSSC 2014,C.Ho,JSSC 2016,B.Liu,TCAS-I 2020T.Seong,ISSCC 2020,Q.Zhang,ISSCC 2023,S.Dartizio,ISSCC 2023Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques37 of 81 2024 IEEE International Solid-St

242、ate Circuits ConferencePseudo Differential DTCD.Xu,ISSCC 2024Dctrl00.5Tdco-0.5Tdco dtcprelative delay dtcnDmax-Dmax0b1(1-4()2)Dctrl2DmaxDctrl2Dmax+b2()2-)Dctrl2Dmax14 inlp(Dctrl)=inln(-Dctrl)=inldiff(Dctrl)=inlp(Dctrl)-inln(Dctrl)=2b1(1-4()2)Dctrl2DmaxDctrl2DmaxDctrl inlp inln inldiffDTC INLDmax-Dma

243、x0even component0,1,2,3,.,31PDreffbTdco0,1,2,3,.,31fb31,30,29,0ref0.5TdcoPDPseudo diff.DTCConv.DTCEven-order INL can be cancelled.a1(1-4()2)Dctrl2DmaxDctrl2Dmax+a2()2-)Dctrl2Dmax14(Dctrl)=inlDctrl00.5Tdco-0.5Tdcorelative delay dtcDmax-Dmax0DTC INLDctrl inlDmax-Dmax0Kenichi OkadaISSCC 2024-Forum 5.3:

244、Low-Power Fractional-N Digital PLL Design Techniques38 of 81 2024 IEEE International Solid-State Circuits ConferenceCascaded Fractional DividerMMDPDLFDTCmainDTCauxDSMauxDSMmain3bit-fcwaux15bit-fcwfracfcwmain+-+-+-reffb dtcmain+inlmain+dtcaux+inlauxdcoD.Xu,ISSCC 2024PLL Output PN dBc/Hz456710101010-1

245、50-140-130-120-110-100-90-80-70-60-50Conv.PLLDither-based PLLelevated random noisef HzSpur power scrambled456710101010-150-140-130-120-110-100-90-80-70-60-50PLL Output PN dBc/Hzf Hz20dB reduction Conv.PLLThis workspur frequency shifted to 12.5MHzPLL Jitter ComparisonConv.DTC-based Frac-N PLL712 fsDi

246、ther-PLL129 fsThis Work119 fsInt-N PLL89fs DPD-less INL mitigation Not dither Pushing spurs to higher offset frequency Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques39 of 81 2024 IEEE International Solid-State Circuits Conference Introduction DTC DCO DTC-based

247、 ADPLL Sampling/Subsampling-switching ADPLL Oversampling PLL ConclusionOutlinesKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques40 of 81 2024 IEEE International Solid-State Circuits ConferenceRing-VCO or LC-VCOLC-VCO A.Mazzanti,et al.,JSSC 2008Ring-VCOA.Abidi,JSS

248、C 2006+30dB betterK.Okada,et al.,VLSI Circuits 2009=+=+*Assumption:#stages=,=,=,=Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques41 of 81 2024 IEEE International Solid-State Circuits ConferenceCMOS OscillatorVDDBIASIBIASRtankVPVN05000200400600Current(

249、A)Amplitude(mV)Fail to oscillating.Rtank1000 700 1300 CMOS DCO Amplitude vs.Current Rtanklimited by process and tuning rangeConv.Low-Power DCO DesignKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques42 of 81 2024 IEEE International Solid-State Circuits ConferenceV

250、AMP 4IBIAS Rtank,P LSLP+Rtank,SkLSLP+)(k2 GTF 4.35Rtank,PAmplitude of Proposed ULP-DCO:Amplitude of Conv.CMOS VCO:Proposed equivalent half circuit:VAMP 4IBIAS Rtank CENVNRPRSOUTNVPOUTPNCoarse:11bitBIASVNVDDCENOUTPVPOUTNIBIASLPLSkkFine:9bitCapacitor bankTF-basd VCOTF-Based Low-Power DCOH.Liu,et al.,I

251、SSCC 2019-107dBc/Hz 1MHz at 2.46GHz Pdc of 107W FOM of-185dBc/Hz Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques43 of 81 2024 IEEE International Solid-State Circuits ConferenceUltra-Compact LC-VCOR.Murakami,EuMC 2010Beneath5%Q dropNormalStacked-spiral Inductor

252、realizes a 20GHz VCO with FoM=-173dBc/Hzby 22um x 22um layout area in 65nm.cons:narrower tuning rangeQ=3 20GHz22m mm22m mmIO bufferVCO coreLC-VCO can replace RO-VCO.Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques44 of 81 2024 IEEE International Solid-State Circ

253、uits Conference Introduction DTC DCO DTC-based ADPLL Sampling/Subsampling-switching ADPLL Oversampling PLL ConclusionOutlinesKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques45 of 81 2024 IEEE International Solid-State Circuits ConferenceMMDIV1st-Order DSMbased C

254、ontroller10b Frac.Phase7b Int.PhaseLoop FilterPhaseOffsetFCWMedium(6b)Fine(10b)Always-onCoarse PLLLMS GainCalibrationTA(X8)4bit 2ps-Res.TA-TDCTDC+DTC:282W52MS/sDCO10bit Isolated Constant-SlopeDTCFBDCO DitherClockX2REF26MHzX2Proposed ADPLLKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digit

255、al PLL Design Techniques46 of 81 2024 IEEE International Solid-State Circuits ConferenceMMDIVMedium(6b)GatedLoop FilterPFDCNTLATCHENDCODCODeadzone(64ps)10bit Isolated Constant-Slope DTCREFFBBBPDSign BitLoop Filter26MHzX2REFFBNarrow-RangeTDCFine(10b)Speed up phase locking rather than frequency lockin

256、g Only 5W static power after phase locking with 4.2s settlingAlways-on Coarse PLLCoarse PLLKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques47 of 81 2024 IEEE International Solid-State Circuits ConferenceDTC+TDCDigitalREF.DoublerSPIMMDDCO880m mm680m mmTSMC 65nm C

257、MOSChip PhotoKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques48 of 81 2024 IEEE International Solid-State Circuits Conference10M1M100k10k-90-100-110-120-130-140-150-160-180-80-70-60-50-40-301K-170w/DoublerDTC142WTA-TDC140WDCO304WDigital*283WDoubler112WTotal981WP

258、ower Consumption26MHz REF w/DoublerFCW:46.96154Jitter:535fsBluetooth channel*Including MMD and Coarse PLLPhase Noise MeasurementKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques49 of 81 2024 IEEE International Solid-State Circuits Conference26MHz REF w/o DoublerF

259、CW:93.92308(Bluetooth channel)Jitter:1.00ps10M1M100k10k-90-100-110-120-130-140-150-160-170-180-80-70-60-50-40-301KPhase Noise MeasurementPower Consumption*Including MMD and Coarse PLLw/o DoublerDTC98WTA-TDC80WDCO285WDigital*190WTotal653W26MHz REF w/o DoublerFCW:93.92308Jitter:1.00psKenichi OkadaISSC

260、C 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques50 of 81 2024 IEEE International Solid-State Circuits ConferenceFractional SpursKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques51 of 81 2024 IEEE International Solid-State Circuits ConferenceL

261、ocking time from 2.429GHz to 2.442GHz(13MHz)2.442GHz2.427GHz-8s12s4.2sLocking TimeKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques52 of 81 2024 IEEE International Solid-State Circuits ConferenceH.LiuISSCC18X.GaoISSCC16A.ElkholyJSSC15D.TascaJSSC11F.W.KuoVLSI17Tec

262、hnology65nm28nm65nm130nm28nmArchitectureIsolated Constant-slope DTC+TDCVariable-slope DTC+TDCVariable-slope DTC+TDCVariable-slopeDTC+BBPDFull range TDCReference26MHz w/Doubler26MHz w/o Doubler40MHz50MHz40MHz40MHzFrequency2.0-2.8GHz2.7-4.33GHz4.4-5.2GHz2.9-4.0GHz2.05-2.55GHzJitterRMS0.53ps1.00ps0.16p

263、s0.49ps0.56ps0.86psIn-band Spur-56dBc-50dBc-54dBc-51.5dBc-42dBcN.A.Power0.98mW0.65mW8.2mW3.7mW4.5mW1.6mWFOM-246dB-242dB-246.8dB-240.5dB-241.3dB-239.3dBComparisonKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques53 of 81 2024 IEEE International Solid-State Circuits

264、 ConferenceTascaJSSC115F.-W.KuoVLSI176ChillaraISSCC141ElkholyJSSC154Y.-H.LiuTCAS-IY.HeISSCC172SaiISSCC16F.-W.KuoESSCIRC15H.-S.KimJSSC13Y.-H.LiuISSCC15-250-245-240-This WorkFoM(dB)Power Consumption(mW)Fractional-N ADPLLThis Work(w/Doubler)This Work(w/o Doubler)ComparisonKenichi OkadaISSC

265、C 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques54 of 81 2024 IEEE International Solid-State Circuits Conference Introduction DTC DCO DTC-based ADPLL Sampling/Subsampling-switching ADPLL Oversampling PLL ConclusionOutlinesKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N

266、Digital PLL Design Techniques55 of 81 2024 IEEE International Solid-State Circuits ConferenceH.Liu,ISSCC 2018 and JSSC 2018 Robust to disturbances Fast settling Low power with good FOMNR-TDC:Narrow-Range TDCNR-TDCLow-Power Digital Sampling PLLKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N

267、Digital PLL Design Techniques56 of 81 2024 IEEE International Solid-State Circuits ConferenceBlocksSpec.JitterPowerDCO-107dBc/Hz1MHz49.8%107uWTDC9ps/LSB27.0%22uWDTC2ps/LSB23.2%23uWMMD&Sampler9bit0.0%218uW Poor power jitter trade-off from the feedback pathSystem Level Estimation of ULP DPLLKenichi Ok

268、adaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques57 of 81 2024 IEEE International Solid-State Circuits ConferenceSubsampling Same transfer function with Sampling DPLL No divider power Less DCO buffer powerNR-DTCNR-DTCNR-TDCNR-TDCLow-Power Digital SubsamplingKenichi OkadaIS

269、SCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques58 of 81 2024 IEEE International Solid-State Circuits ConferenceSubsampling PLL has multiple locking ranges:Cannot recover from large frequency/phase errors Falsely locks to other frequencies(require FLL to monitor freq.errors)Lo

270、w-Power Digital SubsamplingKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques59 of 81 2024 IEEE International Solid-State Circuits Conference Low power and robust phase/frequency acquisition Switching seamlessly without disturb phase locked stateDTCNR-TDCCombine t

271、wo modes into one loop:Proposed Switching FB PathFB can be generated from CKV and REFAKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques60 of 81 2024 IEEE International Solid-State Circuits ConferenceDTCNR-TDCProposed Dead Zone Detector DZ Det.detects large phase

272、error in backgroundH.Liu,ISSCC 2018Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques61 of 81 2024 IEEE International Solid-State Circuits Conference Coarse PLL help fast pull in the DCO phase to reference phaseDTCNR-TDCDuty Cycled Freq.DetectorCoarse PLLKenichi O

273、kadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques62 of 81 2024 IEEE International Solid-State Circuits ConferenceDTCNR-TDCDuty Cycled Freq.DetectorProposed Duty-Cycled FLL(DC-FLL)DC-FLL in backgroundKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Desi

274、gn Techniques63 of 81 2024 IEEE International Solid-State Circuits Conference PLL can regain locked from any frequency disturbances Power can be significantly reducedProposed ULP Fractional-N DPLLKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques64 of 81 2024 IEEE

275、 International Solid-State Circuits ConferenceTSMC 65nm CMOSChip PhotoKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques65 of 81 2024 IEEE International Solid-State Circuits ConferenceFractional-N DPLL Phase Noise-140-120-100-80-60-40-20Phase Noise(dBc/Hz)1K10K100

276、K1M10MOffset Frequency(Hz)Frac.Freq.of 2.404GHz Jitter of 2.8ps Pdc of 265W FOM of-237dB Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques66 of 81 2024 IEEE International Solid-State Circuits Conference*Frequency Disturbances=(FCW2-FCW1)*10MHz=40MHz15sRe-locking

277、Transient MeasurementKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques67 of 81 2024 IEEE International Solid-State Circuits Conference*Conv.Is base on simulationsPower ConsumptionKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniqu

278、es68 of 81 2024 IEEE International Solid-State Circuits ConferenceH.LiuISSCC19Y.-M.HeISSCC17V.ChillaraISSCC14H.LiuISSCC18CMOS Process65nm40nm40nm65nmReference(MHz)10N/A3252Frequency(GHz)2.1-3.11.8-2.52.1-2.72.0-2.8Power(W)265673860980Power Eff.(W/GHz)1Jitter(ps)2.81.981.710.53FOM(dB)-236.

279、8-235.8-236.0-245.6Area(mm2)0.250.180.200.23Comparison TableKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques69 of 81 2024 IEEE International Solid-State Circuits ConferenceH.Liu ISSCC19Ultra-Low-Power Fractional-N PLLKenichi OkadaISSCC 2024-Forum 5.3:Low-Power F

280、ractional-N Digital PLL Design Techniques70 of 81 2024 IEEE International Solid-State Circuits Conference Introduction DTC DCO DTC-based ADPLL Sampling/Subsampling-switching ADPLL Oversampling PLL ConclusionOutlinesKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Technique

281、s71 of 81 2024 IEEE International Solid-State Circuits ConferenceReference OversamplingREFPD Timing fPD=fREFTREFConventional:.J.Qiu,ISSCC 2021,JSSC 2021,ISSCC 2023Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques72 of 81 2024 IEEE International Solid-State Circui

282、ts ConferenceReference OversamplingVCO free run1x sampling PLL-10-20-30-40-50-60-70-80-90-100-110-120-130-140-150 oversampling PLL-77dBc/Hz 10kHzRMS jitter10k,10M:5.79ps1k100100k1M10M10k-160VCO free run1x sampling PLL-10-20-30-40-50-60-70-80-90-100-110-120-130-140-150 oversampling PLL-77dBc/Hz 10kHz

283、RMS jitter10k,10M:5.79ps1k100100k1M10M10k-160REFPD Timing fPD=fREFTREFConventional:.Oversampling:100ps jitter5.8ps jitter .Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques73 of 81 2024 IEEE International Solid-State Circuits ConferenceOversampling PLLJ.Qiu,ISSCC

284、 2021,JSSC 2021,ISSCC 20238MHz CLKFBREFDACDLFMMDDTCFB 2.4GHz DCOCMPCLKPD(fCLKFB=fREF x OSR)32kHz XOfOUTtDTC,nAdaptive LuTs for DAC&DTC Ctrl.21OSRLuT values are automaticallyconfigured using CLKPD.Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques74 of 81 2024 IEEE

285、 International Solid-State Circuits ConferenceOversampling PLLJ.Qiu,ISSCC 2021,JSSC 2021,ISSCC 2023CLKOUTFCWRDACDLFDCOe(t)REFFBfineCLKPDCMP+-PFD+DZDLFcoarseCDAC(n)CNTLMS Gain e(t)CDTC_Frac(n)106DSM QNMMDMain PLL loopCal.loop32kHz XO-+10DTC10CDTC_fine(n)CDTC_coarse(n)118Weight(n)Coarse PLL loopCLKFB(

286、8MHz)10Phase Accum.12256Addr.t1012256Addr.LuTs(OSR banks;OSR=256)8tDTC,nDAC Ctrl.DTC Ctrl.Weight Ctrl.10(Addr.=n)Weight(n)REF+1-1noisy peaknoisy peak0Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques75 of 81 2024 IEEE International Solid-State Circuits Conference

287、Automatic configuration of LuT00.511.52#Reference Cycle00.20.40.60.81Amplitude(V)00.20.40.60.81Amplitude(V)00.511.52#Reference Cycle-74dBcw/Cal.Reference inputDAC outputKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques76 of 81 2024 IEEE International Solid-State

288、Circuits ConferenceAutomatic configuration of LuT00.511.52#Reference Cycle00.20.40.60.81Amplitude(V)00.511.52#Reference Cycle00.20.40.60.81Amplitude(V)-59dBc-71dBcw/Cal.Reference inputDAC outputKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques77 of 81 2024 IEEE I

289、nternational Solid-State Circuits ConferenceOversampling PLL=(),-250-240-230-220-210FoM(dB)Reference Frequency(Hz)10k100k1M10M100MISSCC20ISSCC20ISSCC20ISSCC19ISSCC19ISSCC19ISSCC19ISSCC18ISSCC18ISSCC18ISSCC18ISSCC18ISSCC17ISSCC17ISSCC17ISSCC17ISSCC17ISSCC16ISSCC16ISSCC16ISSCC16VLSI20VLSI20This WorkVL

290、SI19VLSI19VLSI19ISSCC17JSSC17JSSC20JSSC12JSSC19JSSC10LC frac-N PLLRO frac-N PLLLC int-N PLLRO int-N PLLFOM=20log(Jitter/1s)+10log(Power/1mW)FOMRef=20log(Jitter/1s)+10log(Power/1mW)+10log(FRef/100MHz)Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques78 of 81 2024 I

291、EEE International Solid-State Circuits Conference Still many challenges are remained for PLL design.Integer-N PLL design is much easier than Frac-N PLL design if it is just for optimizing FoM.DTC-assisted narrow-range TDC can improve linearity/jitter/power consumption.Oversampling can compensate for

292、 low-frequency reference.ConclusionKenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques79 of 81 2024 IEEE International Solid-State Circuits ConferenceReferencesHanli Liu,et al.,A 265-W Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling

293、 Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,”IEEE Journal of Solid-State Circuits(JSSC),Vol.54,No.12,Dec.2019.Hanli Liu,et al.,A 265-W Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMO

294、S,”IEEE International Solid-State Circuits Conference(ISSCC),pp.256-257,Feb.2019.Hanli Liu,et al.,A Sub-mW Fractional-N ADPLL with FOM of-246dB for IoT Applications,IEEE Journal of Solid-State Circuits(JSSC),Vol.53,No.12,pp.3540-3552,Dec.2018.Hanli Liu,et al.,A 0.98mW Fractional-N ADPLL Using 10b Is

295、olated Constant-Slope DTC with FoM of-246dB for IoT Applications in 65nm CMOS,”IEEE International Solid-State Circuits Conference(ISSCC),pp.246-247,Feb.2018.Hanli Liu,et al.,A DPLL-Centric Bluetooth Low-Energy Transceiver with a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS,IEEE Jou

296、rnal of Solid-State Circuits(JSSC),Vol.53,No.12,pp.3672-3687,Dec.2018.Hanli Liu,et al.,An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS,IEEE International Solid-State Circuits Conference(ISSC

297、C),pp.444-445,Feb.2018.Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques80 of 81 2024 IEEE International Solid-State Circuits ConferenceReferencesHaosheng Zhang,Aravind Tharayil Narayanan,Hans Herdian,Bangan Liu,Yun Wang,Atsushi Shirane,and Kenichi Okada,0.2mW 70

298、fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving-270dB FoM and-66dBc Reference Spur,“VLSI Circuits,June 2019.Aravind Tharayil Narayanan,Ning Li,Kenichi Okada,and Akira Matsuzawa,A Pulse-Tail-Feedback VCO Achieving FoM of 195dBc/Hz with Flicker

299、Noise Corner of 700Hz,“IEEE Symposium on VLSI Circuits(VLSI Circuits),pp.124-125,June 2017.Aravind Tharayil Narayanan,Makihiko Katsuragi,Kento Kimura,Satoshi Kondo,Korkut Kaan Tokgoz,Kengo Nakata,Wei Deng,Kenichi Okada,and Akira Matsuzawa,A Fractional-N Sub-Sampling PLL Using a Pipelined Phase-Inter

300、polator with an FoM of-250dB,“IEEE Journal of Solid-State Circuits(JSSC),Vol.51,No.7,pp.1630-1640,July 2016.Junjun Qiu,et al.,“A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth,”IEEE Journal of Solid-State Circuits(JSSC),Vol.56,No.12,pp.3741-3755,Dec.2021.Junjun Qiu,e

301、t al.,“A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth,”IEEE International Solid-State Circuits Conference(ISSCC),pp.454-455,Feb.2021.Dingxin Xu,et al.,“A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur

302、 and 143.7fs Integrated Jitter,”IEEE International Solid-State Circuits Conference(ISSCC),Feb.2024.Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques81 of 81 2024 IEEE International Solid-State Circuits ConferenceAcknowledgementThis work is partially supported by

303、NICT(JPJ012368C00801),MIC(JPJ000254),STAR,and VDEC in collaboration with Cadence Design Systems,Inc.,Mentor Graphics,Inc.,and Keysight Technologies Japan,Ltd.Kenichi OkadaISSCC 2024-Forum 5.3:Low-Power Fractional-N Digital PLL Design Techniques82 of 81 2024 IEEE International Solid-State Circuits Co

304、nferencePlease Scan to Rate Please Scan to Rate This PaperThis Paper 2024 IEEE International Solid-State Circuits ConferenceHigh-Performance Fractional-N Digital PLLsAshoke RaviWireless Connectivity SolutionsIntelISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs1 of 48Ashoke Ravi 2024

305、IEEE International Solid-State Circuits ConferenceOutlineISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs2 of 48Ashoke RaviMotivationFractional-N All-Digital PLL(ADPLL)system overviewDPLL blocks:Digitally Controlled Oscillator(DCO)Time-Digital Converter(TDC)Digital control loopAlgorit

306、hms for improved phase noise and locking performance MeasurementsSummary&Future Research 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs3 of 48Ashoke RaviEvolution of Wireless StandardsDemand for multi-Gbps traffic in wireless ap

307、plications(e.g.WiFi7,5G)Wider channel BW 320MHzHigher order modulation 4k-QAM OFDM MIMO,carrier aggregation multiple simultaneous chains 802.11-199711b11g/a11n11ac11ax520.010.100003GLTE-A5G4G2G3GPP,Wi-Fi Alliance 2024 IEEE International Solid-State Circuits Conferenc

308、eISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs4 of 48Ashoke RaviTrends in Radio TransceiversStep 1:Architecture optimization(e.g.super-het ZIF)Step 2:Integrate components:external passives,RF+FEMStep 3:Integrate radios with PHY/MAC&ProcessorPrimary driver:cost&form-factor reduction

309、802.11abg External FEM&PLL filter44.60 x59.75x4.9 mm3802.11n 3x3External FEM802.11n 3x3Fully IntegratedS.Gross,RFIC2010802.11ax 2x2Fully Integrated12x16x1.7 mm326.8x30 x3.75 mm3 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs5 of

310、 48Ashoke RaviInductorsNo scaling with processHigh-order(analog)base-band filtersCap density improvesBut SNR&matching limit scalingLO circuits are a major contributorArea Hogs&Scaling in Radios 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N

311、Digital PLLs6 of 48Ashoke RaviIntegration ConsequencesParadigm shift:RF must be designed on lead CMOS processesWhat is required?Digital Radio ArchitecturesDeal with low voltages,more variationsLimited analog enhancements&RF modelsShorter design cyclesNoise from digital circuitsThou shall not limit y

312、ield!Increase digital contentVariation tolerant circuitsOn-die calibration,correction&self-testLess dependence on RF modelsRegulator&isolation strategy 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs7 of 48Ashoke RaviPhase Noise

313、Requirements(WiFi-7)Integrated phase noise -50dBc(SSB)required at 7.125GHz 1x1 RX2x2 RXSNRSSB IPNSNRSSB IPNMCS928-3730-39MCS1133-4235-44MCS1338-4740-49TXEVMSSB IPNMCS9-32-43MCS11-35-46MCS13-38-49 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-

314、N Digital PLLs8 of 48Ashoke RaviFractional-N Digital PLL ArchitecturesDivider-based DPLLDivider-less DPLLDigital FilterTDCFreq WordDCO+REFDigital FilterDCOTDCREFMulti-mod.Freq WordKTDC Residue CancellationSimilar DCO requirementsDesign choices impact TDC resolution,range and linearity R.B.Staszewski

315、,ISSCC 2004Z.Boos,ISSCC 2011 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs9 of 48Ashoke RaviDAC to interface to oscillatorAllows use of legacy LC-VCOsDAC design issuesQuantization&resolutionThermal/Flicker NoiseSignal rangeVara

316、ctor issues:AM-PM conversion limits PNEvolution of DCO from VCOTime-to-DigitalDigital Loop FilterDCODividerref(t)div(t)out(t)VaractorVaractorAnalog controlDAC 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs10 of 48Ashoke RaviTime

317、-to-DigitalDigital Loop FilterDCODividerref(t)div(t)out(t)VaractorVaractorFine controlCoarse controlThermometric arrayxxxxBinary arrayy2y4y2NySegment capacitance into banksBinary ArrayEfficient(#of cells)Potential non-monotonicitySuitable for coarse tuningActive during acquisitionThermometric ArrayM

318、ore cellsMonotonicSuitable for phase locking and trackingDCO:Absorb DAC into Oscillator 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs11 of 48Ashoke RaviPrior Art:Digital Varactor DitheringR.B.Staszewski,ISSCC 2004 dithering to

319、shape quantization noise improved frequency resolutionT.Tokairin,ISSCC 2010 dithering breaks up periodicity for static inputs 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs12 of 48Ashoke RaviPrior Art:Dithering Free DCOFine bank

320、 in tailNo need for Useful for high freq DCOOvercome process limitsSensitive to tail parasiticsMore non-linear=2 0202L.Fanori,ISSCC 2010Classic-RC is shrunk 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs13 of 48Ashoke RaviPropos

321、ed Dual-Core DCONMOS only for low phase-noise and high swingVoltage biased architecture with ultra low noise LDOCommon mode resonance 2f0Flicker noise up conversion reductionReduce Q-degradation through triode operationTank capacitance shared between coresResistively coupled 2 cores for 3dB phase no

322、ise reductionVDDVDDLTANKLTANKCTANKLTAIL,CTAILLTAIL,CTAIL1212 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs14 of 48Ashoke RaviDCO Tuning3 types of thermometer coded capacitor arrays5 coarse units15 fine unitsArray with 255 ultra

323、 fine unitsOptimized for:low rON high Qlarge tuning rangegood matchingcontrolcontrolcontrol255 units dvarThermometric coarse/fine unitThermometric ultra fine unit(dvar)CTANK3 types of thermometric capacitor arrays 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Perfo

324、rmance Fractional-N Digital PLLs15 of 48Ashoke RaviTDC QuantizationDQDQDQVCOREFVCOREF012=1=1=0Delay resolution introduces phase quantization 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs16 of 48Ashoke Ravi*Assumptions:-46dBc SS

325、B Noise,1MHz bandwidth,40MHz referenceRequired TDC resolution 1ps Phase Noise Pareto for Gbps WiFi110-60-55-50-45-40-35-30-25TDC Resolution(ps)Integrated Phase Noise(dBc)TDCVCOREF 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs17

326、 of 48Ashoke RaviFlash TDC TopologiesTDC resolution 3 5ps 43;=NNGateTDCLee,JSSC 1997V/2R/2VCO PathREF PathDQV/2R/2RVTDC=Dudek,JSSC 2000Vernier TDCInterpolating TDC 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs18 of 48Ashoke Rav

327、iRing Oscillator TDCsSTART.QQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDDigital CounterENSTOP.All digital,flash-like with cell reuseVery high dynamic rangeBut uses small number of cellsNoise accumulationDNL is repetitiveDelay stabilization needed 2024 IEEE Interna

328、tional Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs19 of 48Ashoke RaviNoise Shaping in GROsStraayer,JSSC 2008 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs20 of 48Ashoke RaviRec

329、irculating/Beating TDCTDC resolution set by beat frequencyREFVCOD QTROD QD QD Q0321REFVCOTROCLKTROCLKVCOT 43VCOTD Q40=03=02=11=14=0TROTD Q55=1)43(VCOTROTT=VCOTROff=34 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs21 of 48Ashoke

330、Ravi6-bit Beating TDC ExampleREFVCOD QTROD64-Stage Shift RegisterEdge Detection LogicresetFull?OutTROCLKVCOTROTT=6463Re-use delay element to get a linear TDCH.S.Kim,JSSC 2013 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs22 of 4

331、8Ashoke RaviSegmenting for Resolution:Pipeline TDCY-H Seo,VLSI 2011 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs23 of 48Ashoke RaviSegmenting:2-Step TDCTime amplifier resolutionAllows use of standard delaysTiming of mux must b

332、e accurate;arbiter must be fastMismatch of elements degrades results M.Lee,VLSI 2007 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs24 of 48Ashoke RaviTime AmplifiersM.Lee,VLSI 2007Variable delay of latch with near-coincident inp

333、uts amplify time difference 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Digital PLLs25 of 48Ashoke RaviHigh Resolution:Stochastic TDCVCOREFts1tsN11100001-bit1-bittspdfOUTtOUTNSpatial averaging improves resolutionGutnik,VLSI 2000 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 5.4:High-Performance Fractional-N Dig