1、ISSCC 2024SESSION 4High Performance Transceivers and Transmitters for Communication and Ranging4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference1 of 47A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS

2、N.Andersen1,S.Bagga1,J.A.Michaelsen1,H.A.Hjortland1,L.Leene1,T.Skr1,E.Stenersen1,D.T.Wisland1,21Novelda AS,Oslo,Norway2University of Oslo,Oslo,Norway4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference2 of 47Outline Motivat

3、ionApplication examples SoC Overview Transceiver Implementation Application-Level Usage Measurements and Performance Comparison Conclusion4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference3 of 47Outline MotivationApplicat

4、ion examples SoC Overview Transceiver Implementation Application-Level Usage Measurements and Performance Comparison Conclusion4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference4 of 47Motivation Currently UWB is seeing in

5、creased usagePrecise ranging and localization of active tags Inherently high bandwidthAccuracy in rangedetermination Therefore,also a goodchoice for sensingRadar based sensorsPassive targets Novelda AS4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International S

6、olid-State Circuits Conference5 of 47Motivation(Application Examples)Smart homes and buildings Control light and HVAC Must be able to detect a person sitting still,only breathing,at a distanceTypically 10m Challenging sensitivity requirementIllustration Novelda AS4.1:A 79.7W Two-Transceiver Direct-R

7、F 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference6 of 47Motivation(Application Examples)Vital signs Such as breathing,heart rate,and movement Used to infer sleep stages,to detect abnormal breathing patterns,or other health indicators Heart beat detection r

8、equires 30dB greater sensitivity compared to breathingIllustration Novelda AS4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference7 of 47Motivation(Application Examples)Automotive in-cabin sensing Child presence detection La

9、rge metal reflectorsClutter stringent phase noise requirements See through seats,blankets,etc.UWB advantageous over 60GHz and 77GHzIllustration Novelda AS4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference8 of 47Outline Mo

10、tivationApplication examples SoC Overview Transceiver Implementation Application-Level Usage Measurements and Performance Comparison Conclusion4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference9 of 47Self-Contained Radar

11、SoC Two 7.875GHz transceivers(TRX)Angle-of-arrival(AoA)Dynamically constraining the field of view4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference10 of 47Self-Contained Radar SoC Two 7.875GHz transceivers(TRX)Angle-of-ar

12、rival(AoA)Dynamically constraining the field of view4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference11 of 47Self-Contained Radar SoC Common LO Can be injectionlocked through LVDSSynchronize multiple chipsCombine 2 TRXs

13、for 3D or improved angular resolution4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference12 of 47Self-Contained Radar SoC Power managementVoltage regulatorsDeep sleep state CPU for on-chip processing4.1:A 79.7W Two-Transcei

14、ver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference13 of 47Self-Contained Radar SoC Few external components required Two antennas,each with RX and TX(shared RF port)Crystal used for trimming on-chip LOs Decoupling4.1:A 79.7W Two-Transceiver Direc

15、t-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference14 of 47Outline MotivationApplication examples SoC Overview Transceiver Implementation Application-Level Usage Measurements and Performance Comparison Conclusion4.1:A 79.7W Two-Transceiver Direct-RF 7.875

16、GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference15 of 47TRX Timing Overview A common LO clocks both TRXs5.25GHz LC DCO w/a PN of -135dBc/Hz at 10MHz offset Free running in normal operationPeriodic and temperature triggered trimming using the external crystal as

17、a reference 10MHz accuracy needed for regulatory mask compliance No locking or crystal oscillator startup requiredFast duty cycling saves power4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference16 of 47Receiver Frontend(RX

18、FE)Architecture Direct-RF sub-sampling receiverThe band-pass filter(BPF)and LNA band-pass filterthe received 7.875GHz signalThe ADC samples at 2.1GS/s3.75 sub-sampling factor4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Confere

19、nce17 of 47Band-Pass Filter(BPF)Attenuate out-of-band blockers below 6.425GHz,e.g.,Wi-Fi at 5GHz Passive 8th-order double harmonic trap filter with two independently tunable notches4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits

20、Conference18 of 47Low-Noise Amplifier(LNA)43dB combined LNA and pre-amp gain460MHz 3dB bandwidth Reactive feedbackImpedance matchingGain boosting4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference19 of 47Low-Noise Amplifie

21、r(LNA)Adjustable center frequencyCompensate for process variation4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference20 of 47Low-Noise Amplifier(LNA)Programmable gain controlled by a sequencerChanges the gain throughout the

22、 range profile4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference21 of 47Low-Noise Amplifier(LNA)Lowest gain mode used to sample the TX pulseCould be used as a reference to compensate for low-frequency phase noise4.1:A 79.

23、7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference22 of 47Receiver Backend Integration and linearity correction of ADC output10 bits ADC output(approximately 1 bit redundancy)Process up to 192-sample range profile(13.7m)4.1:A 79.7

24、W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference23 of 47Receiver Backend Each bit integrated separately Weights are applied after integrationThe weights correspond to the ADCs CDAC capacitors4.1:A 79.7W Two-Transceiver Direct-RF

25、7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference24 of 47Receiver Backend No multiplier required Correction at 30lower rate 10 less power compared to full rate integration in SRAM4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024

26、IEEE International Solid-State Circuits Conference25 of 47Transmitter(TX)Overview Biphase-coded pulses with Gaussian-like envelopeSpectrum smoothingand coexistence(pseudo random sequence)Biphasing helps tosuppress low frequencynoise and DC in RXFE PRF up to 65.625MHz4.1:A 79.7W Two-Transceiver Direc

27、t-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference26 of 47Transmitter(TX)Overview Baseband generated by weighted drivers controlled by a baseband sequencer Upconversion mixer to Fc=7.875GHzFit regulatory masks with integer frequency multiplication4.1:A 7

28、9.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference27 of 47Transmitter(TX)Overview Baseband generated by weighted drivers controlled by a baseband sequencer Upconversion mixer to Fc=7.875GHzFit regulatory masks with integer frequ

29、ency multiplication4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference28 of 47Transmitter(TX)Overview BPF is shared with the RXFE to save area Regulatory mask compliance without external filtering Helps to suppress TX harm

30、onics4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference29 of 47TX Upconversion LC DCO injection locked to the common LOPeriodically trimmedusing an FLL 5.25GHz/2 3=7.875GHz Figure-of-eight inductor minimizing coupling to

31、the RF port4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference30 of 47TX Baseband Sequencer Driving weighted output transistors Switching scheme with large pulse widthsLess susceptible to PVT 440MHz 3dB bandwidth TX LO use

32、d as clockFine grained resolutionin time4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference31 of 47Outline MotivationApplication examples SoC Overview Transceiver Implementation Application-Level Usage Measurements and Per

33、formance Comparison Conclusion4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference32 of 47Low-Power Mode Time-domaindetection algorithm Detecting subjectsentering the detectionzone(2m)Switches to AoA-mode Using one TRX to s

34、ave power 4 FPS(timed by an RC oscillator)2.2s TRX integration time(low duty cycle)4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference33 of 47AoA Mode Range-Doppler processing Using both TRXs for AoA Tracking subjects insi

35、dethe detection zone Integration time increased to 38.1s with 8 FPSDetect subjects standing or sitting still Range is increased to 3.4mAccurately track subjects leaving the zone4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conf

36、erence34 of 47Outline MotivationApplication examples SoC Overview Transceiver Implementation Application-Level Usage Measurements and Performance Comparison Conclusion4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference35 o

37、f 47Implementation40nm CMOS WLCSP(4.3mm 2.3mm)4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference36 of 47RX Measurements RXFE transfer function and summary Including BPF and ADC4.1:A 79.7W Two-Transceiver Direct-RF 7.875GH

38、z UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference37 of 47Measured TX Pulse Shape Approximately 2.8nspulse length-0.5dBm peak pulse power across 100 Positive and negative TX pulse symmetry500ps/div100mV/div4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC

39、 in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference38 of 47Measured TX SpectrumRegulatory mask compliance w/o external filteringIndustrial temperature range(-40C to 85C)4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Cir

40、cuits Conference39 of 47System Level Measurements PCB module used for application measurements 30mm 5mm Two antennas with 0.5dBi gain Crystal for trimming the common LO and decap4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Con

41、ference40 of 47Current Profile and Power Breakdown Current profile in low power mode with duty-cycling(2.2s integration time for 2m range)79.7W average power consumption(1TRX)4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Confer

42、ence41 of 47 AoA-mode tracking a subject walking in acircle Integration timeincreased to 38.1s with3.4m range and 8 FPS 2RX active,2TX enabled alternatingly Average power consumption was 725.9WAoA-Mode Measurement4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE Int

43、ernational Solid-State Circuits Conference42 of 47Performance Comparison4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference43 of 47Outline MotivationApplication examples SoC Overview Transceiver Implementation Application-

44、Level Usage Measurements and Performance Comparison Conclusion4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference44 of 47Conclusion Self-contained UWB radar SoC in 40nm CMOS 79.7W avg.power in low-power mode Crystal-less o

45、peration for fast duty-cycling Direct-RF receiver with sub-sampling RX and TX shares a single RF port w/o switches Regulatory mask compliant with no external filtering4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference45 o

46、f 47Thank you!4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference46 of 47Acknowledgements Part of this work was supported by SkatteFUNNproject number 308462 We would like to acknowledge the contributions from the algorithm

47、,application,IC,RF,software,and test teams at Novelda for their assistance with measurements4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference47 of 47References1.W.Kim et al.,“A Fully Integrated IEEE 802.15.4/4z-Compliant

48、 6.5-to-8GHz UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28nm Process,”ISSCC,pp.462-463,2023.2.R.Chen et al.,“A 6.5-to-10GHz IEEE 802.15.4/4z-Compliant 1T3R UWB Transceiver,”ISSCC,pp.396-397,2022.3.E.Bechthum et al.,“A 3-10GHz 21.5mW/Channel RX and 8.9mW TX IR-UWB 80

49、2.15.4a/z 1T3R Transceiver,”ESSCIRC,pp.421-424,2022.4.G.Lee et al.,“A 1.125Gb/s 28mW 2m-Radio-Range IR-UWB CMOS Transceiver,”ISSCC,pp.302-303,2021.5.Y.H.Liu et al.,“A 680W Burst-Chirp UWB Radar Transceiver for Vital Signs and Occupancy Sensing up to 15m Distance,”ISSCC,pp.166-167,2019.6.N.Andersen e

50、t al.,“A 118mW Pulse-Based Radar SoC in 55nm CMOS for Non-Contact Human Vital Signs Detection,”IEEE JSSC,pp.3421-3433,Dec.2017.4.1:A 79.7W Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm CMOS 2024 IEEE International Solid-State Circuits Conference48 of 47Please Scan to Rate This Paper4.2:A

51、Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference1 of 26A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Sig

52、nalJongsoo Lee,Jaehyuk Jang,Wooseok Lee,Bosung Suh,Heeyong Yoo,Beomyu Park,Jeongkyun Woo,Jaeeun Jang,Inhyo Ryu,Honggul Han,Jaeyoung Kim,Byoungjoong Kang,Minchul Kang,Hojung Kang,John Kang,Minseob Lee,Danbi Lee,Hyeonuk Son,Suhyeon Lee,Soyeon Kim,Hongjong Park,Sangsung Lee,Jeongyeol Bae,Huijung Kim,Jo

53、onhee Lee,Sangmin YooSamsung Electronics,Hwaseong,Korea4.2:A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference2 of 26Outline Motivations Block Diagram of Chip LO TX RX Measur

54、ement Conclusions4.2:A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference3 of 26Motivations Wi-Fi7(802.11be)standard support Faster and more reliable wireless connectivity Des

55、ign challenges for Wi-Fi7Fulfillment of 4K-QAM EVM requirement Excellent linearity and noise performance320MHz BW for high data rate Demanding wideband(320MHz)and power consumptionIncreasing complexity in circuit design Seamless operation supportReal Simultaneous Dual-Band(RSDB)Multi-link Operation(

56、MLO)4.2:A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference4 of 26Wi-Fi7 Feature UpdateWi-Fi7 FeatureChannel Allocation:67GHz 320MHz BW channels addedSupported BW:160MHz BW(W

57、i-Fi6E)320MHz BW(Wi-Fi7)Modulation Order:1K-QAM(Wi-Fi6)4K-QAM(Wi-Fi7)Multi-link Operation(MLO)STR,Non-STR,EMLSR320320320320320320U-NII-5U-NII-6U-NII-7U-NII-860 x 20MHz5925 MHz7125 MHz5945 MHz6425 MHz6525 MHz6875 MHz29 x 40MHz14 x 80MHz7 x 160MHz3 x 320MHzor6 x 320MHz404040404040404040404040404040404

58、040404040404040404040404020 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2020 20 20 20 20 20 20 20 20 20 202080808080808080808080808080800GHz channel allocation4.2:A Tri-Band Dual-Concu

59、rrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference5 of 26Multi-Link Operation(MLO)Multi-Link Operation(MLO)supportSTR(Simultaneous Transmit-Receive)Non-STREMLSR(Enhanced Multi-Link Single Radio)

60、EMLSR(Enhanced Multi-Link Single Radio)Operation DDBusyDD1x1 Radio 11x1 Radio 11xCh11xCh22x2 on Ch2AP(Concurrent Dual Radio)Ch1Ch2Low LatencyRRCACCAARadio 1Radio 2RSTA(Single Radio)For Data ReceptionChannel Switch Signal4.2:A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX E

61、VM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference6 of 26Block Diagram of ChipSupporting Features 802.11a/b/g/n/ac/ax/be Wi-Fi 2X2 RSDB Multi-link Operation(MLO)Two identical Tri-band Transceiver 2.4GHz Receiver/Transmitter 5/6GHz Receiver/Transmitt

62、er FBRX for DPD/CalibrationLO generations Three high performance PLLs One low power PLLWi-Fi5/6G RadioWi-Fi2.4G Radio76.8 MHzXOABB filter&MUXWi-FiMACAIQZIPPYWi-FiPHYWi-FiLinkPMICRFICBaseband2645/6G FEM5/6G FEM2.4G FEM2.4G FEMMerge 5/6G path5/6G_DA5/6G_LOWL0_5/6G2G_DA2G_LO5/6G_LNAWL0_5/6G2.4G_LNA2.4G

63、_LOMerge 5/6G path5/6G_LO5/6G_FBRX_LNAWL0_5/6G PDET2.4G_FBRX_LNA2.4G_LOFBRX for DPD5/6G_LOPcal_5/6GPcal_2.4GMUXPcal_5/6GMUXPcal_2.4GAnalog I/Q interfaceWL1WL0_2GWL0_2.4G PDETWL0_2.4GMerge 5/6G TX path5/6G_LOWL0_5/6G2G_LOWL0_5/6G2.4G_LOMerge 5/6G RX path5/6G_LOWL0_5/6G PDET2.4G_LOFBRX for DPD 5/6G_LO

64、Pcal_5/6GPcal_2.4GMUXPcal_5/6GMUXPcal_2.4GAnalog I/Q interfaceWL0WL0_2.4GWL0_2.4G PDETWL0_2.4GWL0/1_2.4GWL0_5/6GWL1_5/6GWL0/1_LPWL0/1 CommonTemp.SensorLDOBPLLBiasXOsc4.2:A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEE

65、E International Solid-State Circuits Conference7 of 26LO ArchitectureSampling analog PLLHigh-gain sampling phase detector for lower in-band noiseHigh-performance VCO with a dual-core option to halve the phase noise3X or 2.5X LO clock multiplier to avoid TX pulling and to reduce VCO tuning rangeLow-p

66、ower digital PLLAll digital PLL for low-power and smaller areaSub-sampling topology and low-power DCO with no feedback divider to save divider powerx2/1 or/2MMDIVSampling analog PLLSampling PDDTCReferenceclock doublerFLOFrefGM cellDIV2TDCDTCFLOFrefDigitalLPFIQ genHigh-performance VCOLow-power DCOLO

67、clock multiplierLow-power digital PLL4.2:A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference8 of 26LO Architecture for Fractional Spur ReductionFraction Spur Reduction DTC no

68、n-linear calibration(NLC):LMS algorithm using a 1-bit phase error sign extraction circuitDC offset of 1-bit comparator 1-bit V DAC with a modulator is usedUp/down mismatch of 1-bit V DAC Gain coefficient of each polarity is optimizedMMDIVDTCFREFVrefGmDTC codeVsmpX2SPDCalibration for DTC+-+1-1VREF_ca

69、lV-DACDSMPhase error sign(+1/-1)Vsmp+1-1DTCNLCDTCGain calPhase error sign extraction circuitReconfigurable LC VCO4.2:A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference9 of 2

70、6Spur Generation by V-DAC Mismatch When V-DAC UP/DN current mismatch existsIf PLL is in lock state,average phase error sign=0DAC input UP/DN signal ratio 1:1 Average phase error sign 0 Inaccurate phase error sign generation PLL digital calibration accuracy degradationtVref_calCase of(IUP IDN)and(IUP

71、 IDN)UPHOLDDNPhase error sign(+1/-1)tCase of(IUP IDN)+1-1-1+1+1+1+1+1mean(Vsmp)mean(Vref_cal)tUPDNIUPIDNVref_calV-DACVsmpVref_calDSMPhase error sign(+1/-1)IUP IDNUP:DN 1:1mean(phase error sign)0mean(DSM input)0UP/DNDSM input4.2:A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving-46dB TX/

72、RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal 2024 IEEE International Solid-State Circuits Conference10 of 26V-DAC Mismatch CompensationV-DAC UP/DN current gain is individually calibrated Average phase error sign 0More accurate DTC non-linearity calibration especially for spur channelsVref_calCa

73、se of(IUP 60dB To achieve high SNR,control the gain through DA and PA while maintaining a fixed gain for DAC and ABB DA should have a 60dB DR,however isolation is critical issue in the low-power range TX_ABBLOIPLOIN LOQP LOPNMIX-DAInter-stageDA w/comp.capDA_OUTDAC4.3:A 43mm2Fully Integrated Legacy C

74、ellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference18 of 39DA DR Improvement AC shorts in DA(OFF cells):Leakage through Cdsin DA OFF cellsCommon-source drain short for n41(MHB)-Common-gate cross-cou

75、pled pair for n96(NRU)-SW2CcompCcompDA unitSW1VcgVcsVcgCCCPSW2CcompCcompDA unitSW1VcgVcsVcgCCCPSW2CcompCcompDA unitSW1VcgVcsVcgCCCPSW2CcompCcompDA unitSW1VcgVcsVcgCCCPSW2CcompCcompDA unitSW1VcgVcsVcgCCCPSW2CcompCcompDA unitSW1VcgVcsVcgCCCPTX_ABBLOIPLOIN LOQP LOPNMIX-DAInter-stageDA w/comp.capDA_OUT3

76、2 DA unitsDA_OUTNDA_OUTPDA_INNDA_INPDACSW2CcompCcompDA unitSW1VcgVcsVcgCCCPCcompSW2CcompCcompDA unit SW1VcgVcsVcgCCC Flatness improvement in 100MHz:Compensation capacitors(Ccomp)are added to the input of each DA cell to maintain the resonant frequency-Helps maintain band flatness over 100MHz with DA

77、 gain control 4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference19 of 39DA DR Improvement AC shorts in DA(OFF cells):How Cds-induced leakage is countered by the

78、AC short in the DA off cellIn n41,CSDS switches(SW1)are incorporated “Turn ON”when DA off cell In n96,CGCC pair(CCC)are introduced neutralized Cds,enhance stability IN_PIN_NOUT_POUT_N(+)(-)CG:Cross-coupled pairCCCCdsCdsVcgVcgCG stageVcgDA_ONVcgDA_OFFac shortCS:Drain shortac openDA_INPDA_INNDA_INPDA_

79、INNSW1SW1M1M2M1M24.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference20 of 39DA DR Improvement in n41 Common-Source Drain short switches(SW1):-14dB improvement in

80、isolation-10.9dB improvement in dynamic range4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference21 of 39DA DR Improvement in n96 Common-Gate Cross-coupled pair:-1

81、0.7dB improvement in isolation-10dB improvement in dynamic range4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference22 of 39DA Band Flatness Improvement in n96 Com

82、pensation Capacitor(Ccomp)in DA cell input:Resonant frequency shifts to higher frequency when DA cell is turned off without Ccomp variations in band flatness with DA gain control Maintain resonant frequency with Ccomp,flatness is improved below 0.5dB4.3:A 43mm2Fully Integrated Legacy Cellular and 5G

83、 FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference23 of 39Outline Motivations Block Diagram of Chip De-sense(LB,MHB)TX Dynamic range&Flatness FBRX Isolation LO current&size Measurement Conclusions4.3:A 43mm2Full

84、y Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference24 of 39FBRX Isolation Internal DPST(Dual-pole single-throw):Time sharing,EN-DC supports,BoM cost reductionEnsuring isolation

85、between two ports is crucialFBRX1FBRX0FBRX20)DedicatedFBRX01)With external DPSTDPSTDPSTFBRX1FBRX0DPSTDPSTFBRX12)With internal DPST(Proposed)LPAMIDANT0LNAPAFrom TX0CPL_TX0LPAMIDANT1LNAPAFrom TX1CPL_TX1LPAMIDANT2LNAPAFrom TX2CPL_TX2RFICRFICRFIC4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF

86、Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference25 of 39FBRX Isolation Previous FBRX architecture:LB to NRU bands(450MHz 7125MHz)IQ RF blocks with 50%LO duty for reducing LO current and channel flatness Pseudo-differe

87、ntial structure to reduce chip sizeTwo RF paths are duplicated(8 attenuators&8 LNAs)chip size TIAADCRF_PATH1ATT.ATT.ATT.ATT.LNALNALNALNASW3Previous:2x ATTs and LNAsRF_PATH0ATTATTATTATTLNALNALNALNASWMixer4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting In

88、ter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference26 of 39FBRX Isolation Proposed FBRX architecture:Pseudo-RF path connects to other port Size reduction Unwanted leakage applied only to pseudo-RF path Isolation Pseudo-RF path GND connects to RF path GND thro

89、ugh SW5Unwanted leakage applied to both RF paths Isolation 4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference27 of 39FBRX Isolation Measurement:Isolation is impr

90、oved by 14dB in n1(target:-30dB)and by 10dB in the other bands,especially at higher frequencies4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference28 of 39Outline

91、Motivations Block Diagram of Chip De-sense(LB,MHB)TX Dynamic range&Flatness FBRX Isolation LO current&size Measurement Conclusions4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State

92、Circuits Conference29 of 39Wide-Range RXDCO Wide-Range RX LC DCO:Extended the frequency range of the LC DCO up to 8400MHzAllowing support for n77 with DIV2 instead of SSPLL-30%current consumption reduction Covered frequency range extensionADPLL(LC HB DCO)46005380MHzn77(4200MHz)SSPLL(Ring Oscillator)

93、ADPLL(LC WR DCO)46008400MHzn77(4200MHz)DIV24.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference30 of 39Wide-Range TXDCOCovered frequency range extensionLMB DCO(LC

94、DCO)LMB(27924050MHz)HB(46005584MHz)HB DCO(LC DCO)DIV2WR DCO(LC DCO)DIV2LMHB(27925584MHz)Wide-Range LC DCO:LMB/HB LC DCOs are merged 47%size reduction Simplified buffer chain decrease in current consumption 4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting

95、 Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference31 of 39HFTC Hybrid Fine-Tune Capacitor Bank:Fine-tune capacitor bank 30%size reduction OFF-parasitic capacitance 50%reduction Facilitating the implementation of the WR-DCOFine-tune capacitor bankLSB capac

96、itor bankMSB capacitor bank32 arrayx4x4x4x432 arrayx4x4x4x4x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x18 arrayx1x11 array5 arrayDithering cell(b)Hybrid fine-tune capacitor bank with unit cell and dithering cell(a)Fine-tune capacitor bank with 32 X

97、32 arrayx1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x132 arrayUnit cell4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference32 of 39Outline Motivations Block Diagram of Chip De-s

98、ense(LB,MHB)TX Dynamic range&Flatness FBRX Isolation LO current&size Measurement Conclusions4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference33 of 39Measurement

99、s RXS11 shows under-10dB across all target frequenciesCINR exceeds larger than 38dB in 100MHz BW for n41,n77 and n794.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Confe

100、rence34 of 39Measurements TX ACLRMeasured at+6.3dBm Pout in the n77 band with 100MHz,1K-QAM,full-RB ACLR exhibits-45.0(L)/-41.3dBc(R)100MHz,1K-QAM,Full-RBPout=6.3dBmACLRL=-45.0dBc,ACLRR=-41.3dBc4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band

101、7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference35 of 39Measurements RX/TX EVMRX EVM shows 0.8%(-41.9dB)TX EVM shows 0.96%(-40.3dB)4.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM

102、2024 IEEE International Solid-State Circuits Conference36 of 39Chip Photograph43.05mm24.3:A 43mm2Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 44 MIMO with 1K-QAM 2024 IEEE International Solid-State Circuits Conference37 of 39Comparison Tables

103、This work ISSCC 2021 1VLSI 2020 2ISSCC 2020 3ISSCC 2019 -5-6000450-59252G,3G,4G,LTE-A,SA/NSA FR1 NR2G,3G,4G,LTE-A,SA/NSA FR1 NR2G,3G,4G,LTE-A,SA/NSA RF1 NR2G,3G,4G,LTE-A,SA/NSA FR1 NR2G,3G,4G,LTE-A,SA/NSA FR1 NR3.0525.749.7539.8438.40144All DigitalAll

104、DigitalAll DigitalAll DigitalDL Digital/UL AnalogDL path#246182014Sensitivity(dBm)-101(n28,10M)-100.8(B20,10M)-101-100.9(n78,10M)-99.8(B7,10M)EVM(%)0.8(n77,100M)1.37(80MHz)2.6(80MHz)-7070705570SAW-lessYesYesYes-YesUL path#32232Pout(dBm)6.4(n77,100M)7.2(n78)5(n77)65(n77)EVM(%)0.96(n77,100M)1.3(n78)2(

105、n77)2 1ron&roffVDDGNDrprnVinrpVDron&roffVDDGNDRegular Operation Proposed Operationroff=rnron,avg/roff 1k k roff=rn rnNonlinear factor 1Nonlinear factor 2 Nonlinear factor 1:time-variant ron roffdue to input rising/falling time Nonlinear factor 2:output voltage VDfurther impacts ron Linearization:inc

106、rease switched-off resistance roff=rnrn4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference11 of 28Outline Background Operation Principles of Proposed 6-Phase 1/3-Duty-Cycle-LO D

107、TX Circuit Implementation Measurement Results Conclusions 4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference12 of 28Proposed 6-Phase 1/3-Duty-Cycle-LO DTX ArchitectureHighly-in

108、tegrated DTX:DBSP,MPLG,6-phase cell-reused DPA and SPIMultimode DBSP with flexible up-sampling,4-to-6-phase conversion and power control MPLG for accurate and low-noise 6-phase LO generation with only 1x input LO freq.6-phase 1/3-duty-cycle-LO DPA for better Pout,efficiency,HR3 and linearityIBB/QBBS

109、erial-Input-to-Parallel-OutputIBB ZOH 2fCLK ZOH 2 FIR /NN1N2PMPFDCPILROVCDLVctrlLO Input1/2-to-1/3 Duty-Cycle LO Gen.Multi-Phase LO Generator(MPLG)QBBIup FIR QupQuadarature to 6-Phase ConversionFine LO1-6Coarse LO1-6LO1-66-to-2MUXLOiLOi+1Multimode Digital Baseband Signal Processing(DBSP)RF OutputPro

110、posed Highly-Integrated 6-Phase DTX with PAE,Pout and HR3 Enhancement DPA1DPA2SPI6-Phase Cell-Reused DPA4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference13 of 286-Phase Cell-R

111、eused DPA(1/2)Two identical sub-PA(N1&N2)with cell-reused operation Sub-PA structure:14-bit including 8-bit MSB and 6-bit LSB 16 hybrid groups(G15-0)and a binary group(G16)Hybrid group:7 thermo-coded cells(T6-0)and 3 binary cells(1 Bit5 and 2 Bit4)Output PCT power combiner for compact size and wideb

112、and coverage4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference14 of 286-Phase Cell-Reused DPA(2/2)DN1LOiDN2LOi+1DN1RSTDN2RSTLevel ShifterLO1P1LO2P2LO1P1RLO1P1VDD2VDD1VDD1LO2P2L

113、O1P1RNMOS Size Ratio=11:9Unit PA Cell SchematicDelay Compensation(RST at high voltage for normal operation)Output StageLinearization Effect NMOS path is divided into two branches with the ratio of 11:9 AM-PM distortion is reduced by half with the linearization technique4.4:A Highly-Integrated 6-Phas

114、e Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference15 of 28High-Accuracy 6-Phase LO GenerationLO phase error degrades HR3 performance Target:HR3 45dBc d(%)HR301-145dBc-0.30.3d 0.3%1LOiLOi+1LOiLO1Duty Cycle=1

115、/3+dABMPLGLO1/2-to-1/3 Duty CycleDPA1DPA2RLMatching NetworkCLOiLOi+1Phase=60+FreqLO FFTfLO3fLO5fLOResidual 3rdharmonic45dBc （).d(%)0.314.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits C

116、onference16 of 28Multi-Phase Injection-Locking(MPIL)Break the trade-off between phase accuracy and jitter Z.Wang,ISSCC 2021 Achieve low phase error across wide frequency range Tune foexternally for lowest jitter and frequency tracking against PVT4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Tr

117、ansmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference17 of 28MPIL-Based Multi-Phase LO Generator DLL generates injection signals DLL tunes the stage delay in VCDL and ILRO synchronically ILRO corrects phase error with MPIL 45dBc HR3

118、at 6dB PBO over 0.7-2.5GHz4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference21 of 28At fLO=1.7GHz:AM-AM1.6dB,AM-PM11.9Measured DTX CW Performance DTX AM-AM and AM-PM nonlineari

119、tiesAt fLO=0.9GHz:AM-AM0.5dB,AM-PM5.5AM-AM(dB)0.9GHzAM-PM(deg)0.9GHzAM-AM(dB)1.7GHzAM-PM(deg)1.7GHz4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference22 of 28Measured DTX Modula

120、tion Performance LTE 20MHz 64QAM 0.89GHz(w/o calibration):24.2dBm Pavg,27.1%average SE at -25dB EVM-36.5dB EVM at full-scale quantization EVM degrades due to signal clipping 40dB dynamic range with EVM-25dB Pavg=23.7dBmEVM=-26.3dBEVM=-25dBPavg=24.2dBmAverage SE=27.1%w/o Clippingw/Clipping4.4:A Highl

121、y-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference23 of 28Measured DTX Modulation Performance Pavg=21.9dBmEVM=-28.6dBw/o Clippingw/ClippingEVM=-28dBPavg=22.5dBmAverage SE=14.0%OFDM 40MHz

122、256QAM 1.76GHz(w/o calibration):22.5dBm Pavg,14.0%average SE at -28dB EVM 40dB dynamic range with EVM 45dBc4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference25 of 28Comparison

123、with Prior WorksThis WorkISSCC21 1ISSCC20 2ISSCC22 3JSSC23 4JSSC17 6Architecture6-phase with cell reuse and 1/3 duty-cycle LOQuadrature with 4-way Doherty combinerQuadrature SCPAPolar with 4-core DPAPolar with reconfigurable transformer16-phase SCPAFreq.(GHz)0.9/1.75.42.22.4-2.5(LB)/5.1-7.1(HB)21.8P

124、eak Pout(dBm)28.3/27.727.413.028.2/27.832.6726Peak SE(%)41.0/28.5(DTX)30.66(DTX)NA25*(DPA)35.5(DPA)24.9(DPA)HR3(dBc)45NANANANANAModulation SignalLTE 20MHz 64QAM/OFDM 40MHz 256QAMSingle-Carrier 120MHz 64QAM 802.11ax 40MHz 1024QAM802.11ax 40/160MHz10MHz 1024QAM 2.4GHzLTE 10MHz 64QAMPavg(dBm)24.2/22.51

125、7-3.020.9/18.025.54 20.9SEavg(%)27.1/14.0(DTX)19.2(DTX)1(DPA)10*32*8.4/5*6*NACalibrationNoYesNoYesYesYesVoltage(V)1.1/2.211.21.21.1/2.51.5/3Process28nm40nm65nm16nm40nm130nm Core Size(mm2)0.86(DTX)1.5(DTX)0.26(DPA)1.2(DTX)0.99(DPA)3.78(DPA)4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitt

126、er Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference26 of 28Outline Background Operation Principles of Proposed 6-Phase 1/3-Duty-Cycle-LO DTX Circuit Implementation Measurement Results Conclusions 4.4:A Highly-Integrated 6-Phase Cell-Reuse

127、d Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference27 of 28Conclusions A 6-phase cell-reused DTX using 1/3-duty-cycle LO signals for harmonic rejection is proposed.A 6-phase cell-reused DPA with Doherty load modulation

128、and linearization techniques for higher Pout,SE and better linearity.MPIL architecture is introduced as accurate and low-noise multi-phase LO generator.The DTX achieves:Wide frequency coverage of 0.8-2.4GHz Peak Pout of 28.3dBm with 41.0%SE 0.9GHz 45dBc HR3 at 6dB PBO over 0.7-2.5GHz 0.86mm2core are

129、a,40dB dynamic range w/o calibration4.4:A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference28 of 28Acknowledgements We would like to thank the State Key Laboratory of Integrated Chi

130、ps and Systems at Fudan University for measurement supports.We would like to thank group members of Fudan WiCAS lab for technical discussions and supports.This work was supported by the National Natural Science Foundation of China under Grant 62322105.4.4:A Highly-Integrated 6-Phase Cell-Reused Digi

131、tal Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection 2024 IEEE International Solid-State Circuits Conference29 of 26Please Scan to Rate This Paper4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid

132、-State Circuits Conference1 of 17A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOIJohn Zhong,Konstantinos Vasilakopoulos,Antonio LiscidiniUniversity of TorontoAnalog Devices Inc.4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-

133、35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference2 of 17Outline Quantized Analog Signal Processing Quantized Transmitter(QTX)Building BlocksCharge-based DAC(CDAC)Passive Switch Capacitor Filter(PSCF)Power Mixer&LO Generation QTX Measurement ResultsModulate

134、d Signals(64-QAM&256-QAM)Duo Channel Transmission(64-QAM)4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference3 of 17Quantized Analog(QA)Signal ProcessingSignal sliced in N-path exploiting DC

135、 offsets at input of an array of amplifiersAt any given time,some slices are saturated and some unsaturatedSignal can swing above the supply(virtually)and only unsaturated slices introduces analog noise For a given power QA approach can outperform analog in terms of SNR by a factor NJ.Musayev et al.

136、,EL 2018 4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference4 of 17From Traditional TX to QTXA TX analog front-end composed of DAC+LP Filter(passive switched capacitor topology)Signal is sl

137、iced in digital domain with digital offsets and 6-bit saturated adderSignal is recombined at RF after the up conversion in current domain by quantized power mixers4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and KT/LSB2),2(211)2,322(26)2 Ctot,A=32 Ctot,QA PA=32 PQA#o

138、f slices#of bits4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference6 of 17Analog noise in QTXJ.Musayev et al.,EL 2018 In a QA system any noise added after the slicing does not reach the out

139、put if slice saturates(i.e.no gain)Having a virtual swing N times the supply allow to have in each path N2noise for a target SNRFilter can be scale down by a factor N2compared to the analog casePower and area saving is a factor N by having N paths4.5:A Reconfigurable,Multi-Channel Quantized-Analog T

140、ransmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference7 of 17QTX Building Blocks DAC 6-bit capacitive DAC segmented(4 Bin+3 Therm)with unit capacitance Cs,0=2.9fF limited by parasitic.Total area of 32 DACs is 5.9pFNo split/attenuation capacitor

141、architecture required Less number of bits allow also faster sampling=052 26 1 Vasilakopoulos,SSCL 20204.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference8 of 17QTX Building Blocks PSCF In t

142、he PSC Filter CIsize and area is set by the noise which is scaled down by factor of N thanks to QACItunable from 155fF to 485fF while CS=180fF(set by the DAC)Bandwidth tunable from 10MHz to 50MHz,with max=1.5GHzLulec et al.,TCAS2 2019 1(1+)34.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmi

143、tter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference9 of 17QTX Building Blocks Power MixerPower Mixer(Gilbert Cell)operates differently if a slice is saturated or unsaturatedCascode(M2,M6)help to sink constant current for saturated slicesSlice unsat

144、urated(M1 and M5 operate in saturation region)Slice Saturated(M1 and M5 operate in triode region)4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference10 of 17QTX Architecture and recombinatio

145、n I and Q path and QA slices are all recombined in current domain into an on-chip transformerEach slice have a LO/channel select signal to choose between different LO inputs from the multiplexer(Mux)QA TX can allocate a portion of the slices to a different LO for dual-carrier operation4.5:A Reconfig

146、urable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference11 of 17QTX Die Micrograph+Area/Power BreakdownIntegrated on GlobalFoundries 22nm FDSOICore area occupies 0.38mm2(excl.memory nor transformer)Low baseba

147、nd power consumptionClocking+CDAC 25%total power4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference12 of 17QTX Measured Modulated SignalsQTX achieves-56dBc ACLR2&1.9%EVM with 64-QAM PRBS4.5

148、:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference13 of 17QTX Measured Duo-Channel OperationQA TX enable duo/multi-channel operation with 2 LOs4.5:A Reconfigurable,Multi-Channel Quantized-Ana

149、log Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference14 of 17QTX Slice Mismatch and CalibrationImpact of mismatches can be minimized through:Layout and slice area(mismatch obtained less than 0.5dBm)Calibration acting only on the QA offsets

150、 as shown in previous works Q.Yu,OJ-SSCS 2022,J.Y.Kim,OJ-SSCS 20224.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference15 of 17Comparison With Other Works4.5:A Reconfigurable,Multi-Channel Qu

151、antized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference16 of 17ConclusionA quantized analog-based TX was designed,fabricated and testedSQNR and analog noise improves by addition of more slices Smaller DAC and baseband filter saves

152、 significant silicon areaFaster sampling switches allows better baseband channel reconfigurability Multi-channel transmission possibleHigher flexibility than analog-systems(multi-carrier functionalities)4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference17 of 17Thank You!Questions?4.5:A Reconfigurable,Multi-Channel Quantized-Analog Transmitter with-35dB EVM and-51dBc ACLR in 22nm FDSOI 2024 IEEE International Solid-State Circuits Conference18 of 17Please Scan to Rate This Paper