1、SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceCalibration Techniques in PLLsSalvatore LevantinoChair Professor of Electrical EngineeringPolitecnico di Milano,Italysalvatore.levantinopolimi.itSan Francisco,February 18,2023S.LevantinoCalibration Techniques in PLLs1 of 95SpeakerVi

2、deo 2024 IEEE International Solid-State Circuits Conference Digitally-assisted analog circuits Fundamentals of phase-locked loops Fundamentals of adaptive filtering Calibration examplesS.LevantinoCalibration Techniques in PLLsOutline2 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits Co

3、nference Why to assist or replace analog circuits?To exploit low power and small area of digital gates in scaled CMOSS.LevantinoCalibration Techniques in PLLsDigitallyAssisted Analog Circuits(1 of 2)Inferred from TSMC/Intel reports3nm5nm90nm65nm40nm28nm20nm16nm10nm7nmYearDensity MTr/mm2About 10 x in

4、 transistor density in 10 years3 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits Conference Why to assist or replace analog circuits?To exploit low power and small area of digital gates in scaled CMOSTo correct nonlinear behavior and mismatch of analog circuitsS.LevantinoCalibration T

5、echniques in PLLsDigitallyAssisted Analog Circuits(2 of 2)B.E.Boser,2004SystemIdentificationModulationParametersADCAnalognonlinearityDigitalinverse4 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits Conference Digital assistance Enables minimalistic design of analog circuitsImproves ene

6、rgy efficiency and accuracyS.LevantinoCalibration Techniques in PLLsBenefits of Digitally AssistanceB.Murmann,2006MinimalistADCMinimalistSignal ConditioningDigitalPost-ProcessingMinimalistDACMinimalistSignal ConditioningDigitalPre-ProcessingDigital ProcessingAnalog Media and Transducers5 of 95Fundam

7、entals of Phase-Locked LoopsSpeakerVideo 2024 IEEE International Solid-State Circuits Conference GeneralityInteger-NFractional-N Applications ImplementationsCharge-pump analog PLLTDC-based digital PLLS.LevantinoCalibration Techniques in PLLsFundamentals of Phase-Locked Loops:Outline7 of 95SpeakerVid

8、eo 2024 IEEE International Solid-State Circuits ConferenceA voltage-controlled oscillator(VCO)slaved to a reference oscillatorS.LevantinoCalibration Techniques in PLLsWhat is a Phase-Locked Loop?8 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceThe frequency of the VCO(Fo)fo

9、llows the frequency of the input(Fi)S.LevantinoCalibration Techniques in PLLsPLL as“Frequency Follower”VCOPhase DetectorMathematicalModelPhase-Locked Loop9 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceAt steady state,constant phase shift between in(t)and out(t)signalsS.Le

10、vantinoCalibration Techniques in PLLsPhase Alignment in a PLL10 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA digital counter(i.e.,a frequency divider)in feedbackOutput frequency Fois digitally controlled by the integer N:Fo=N FrS.LevantinoCalibration Techniques in PLLsI

11、nteger-N Frequency Synthesis11 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceThe PLL converts a digital word N into a clock whose frequency is proportional to N(as a D/A converter does from digital to voltage/current)S.LevantinoCalibration Techniques in PLLsPLL as”Frequenc

12、y DAC”12 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA modulator dithers MC to achieve fractional division:Fo=(N+m)FrIn other words,we are realizing a-frequency-DACS.LevantinoCalibration Techniques in PLLsFractional-N Frequency SynthesisG.C.Gillette,1969T.A.D.Riley,19931

13、3 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMore on Fractional-N Frequency SynthesisS.LevantinoCalibration Techniques in PLLsThe signals ref(t)and div(t)are aligned only on averageTheir relative phase shift e(t)is given by the integral of the quantization error MC(t)-F

14、CWUnwanted tones appear in the PLL output spectrum(fractional spurs)Case of a 1storder 14 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA Calibrated DAC to Mitigate NoiseS.LevantinoCalibration Techniques in PLLsIn principle,the periodic quantization error can be cancelled

15、outThe DAC requires calibration to match the gain of the divider/PD cascade1storder Quantization errorDana 7000,1973Pamarti,2004Temporiti,200415 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits Conference Clock multiplicationFixed frequency multiplication factorE.g.,clock generator for

16、 an A/D converter Frequency synthesisProgrammable frequency multiplication factorE.g.,local oscillator of a wireless transceiver Skew suppressionPhase aligning an internal clock to an I/O clock Clock recoveryExtract clock frequency from incoming data stream FM modulation/demodulationS.LevantinoCalib

17、ration Techniques in PLLsCommon Applications of PLLs16 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceComplex QAM schemes at mmW require low LO phase noiseE.g.,Integrated PN -36dBc,or Absolute jitter 90 fs(5G NR at 28 GHz)S.LevantinoCalibration Techniques in PLLsPLL Applica

18、tion:Frequency SynthesisDuplexerBPFLNABPFPALODownconversionUpconversionA/DD/ADigital basebandprocessor17 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techniques in PLLsAnalog Charge-Pump PLLWidely adopted in industryJ.M.Laune,US3714463A,197318 of 95

19、SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceThe analog filter takes up large area and suffers from leakage currentThe charge pump has mismatches and limited output resistance,adds noiseArea,power,design cost do not scale down in new CMOS nodesS.LevantinoCalibration Techniques

20、 in PLLsAnalog Charge-Pump PLL:ShortcomingsPhase DetectorrefdivMulti-ModulusDividerVCOoutfcwCoarse TuningDQRDQRCPupdnFilter19 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceFrom Analog to Digital PLLsS.LevantinoCalibration Techniques in PLLs20 of 95SpeakerVideo 2024 IEEE In

21、ternational Solid-State Circuits ConferenceMore-Intensively Digital S.LevantinoCalibration Techniques in PLLsR.B.Staszewski,ISSCC 2005C.M.Hsu et al.,ISSCC 200821 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceTime-to-Digital ConverterS.LevantinoCalibration Techniques in PLL

22、s22 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceDigitally-Controlled OscillatorS.LevantinoCalibration Techniques in PLLs23 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceDigital Loop FilterS.LevantinoCalibration Techniques in PLLsE.g.,FIR filter

23、24 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA digital filter replaces the bulky analog oneCharge pump is absent(less noise,power,area)More friendly to calibrationTDC and DCO introduce quantization and truncation noiseS.LevantinoCalibration Techniques in PLLsTDC-based

24、Digital PLL:pros and consrefdivoutfcwekwkTDCDCODigitalLoopFilterMulti-ModulusDividerPhase DetectorDigitalDigital25 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceCancellation of Quantization NoiseS.LevantinoCalibration Techniques in PLLsUnlike in the CP case,quantization no

25、ise can be accurately canceled out Cancellation requires gain calibration of H(z)to match divider+TDC gain26 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMathematical modelS.LevantinoCalibration Techniques in PLLsQuantization noise is cancelled outif a0=KtdcTv0 modulatorF

26、requency dividerFilterH(z)27 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceSummaryA phase-locked loop is a“frequency follower”.Input are output phase aligned on average.A frequency synthesizer,i.e.,a PLL with a frequency divider in feedback,is essentially a“frequency DAC”.

27、It can multiply the input frequency by an integer or a fractional factor.In a fractional-N frequency synthesizer:Quantization error appears as fractional spurs in the output spectrumQuantization error can be cancelled out by means of a background calibration tracking the system gainThe most typical

28、PLL implementation is the charge-pump PLLDigital PLLs based on TDCs benefit from the elimination of the analog filter and the charge pump and are more friendly to calibrationS.LevantinoCalibration Techniques in PLLs28 of 95Fundamentals of Adaptive FilteringSpeakerVideo 2024 IEEE International Solid-

29、State Circuits ConferenceAdaptiveFilterAdaptationAlgorithmekxkykdk Filter coefficients adjusted to estimate an unknown quantity dk in an input signal xkS.LevantinoCalibration Techniques in PLLsAdaptive Filters Solve an Estimation Problem30 of 95SpeakerVideo 2024 IEEE International Solid-State Circui

30、ts ConferenceS.LevantinoCalibration Techniques in PLLsGeneral Adaptive Filter Problem The filter estimates dk from xk,minimizing a cost function J If xkvaries,the adaptation algorithm updates the filter coefficientsxydStatic caseAdaptiveFilterAdaptationAlgorithmInput correlated to dkEstimation error

31、SignalestimationDesiredSignalekxkykdk31 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techniques in PLLsLinear Estimation CaseAdaptive FilterAdaptation Algorithm Linear FIR filter with Mcoefficients w=w1 w2 wMas adaptive filter The vector wis determi

32、ned recursively with search direction p and step ekxkykdkw2 kw1 kw3 kwM kwk=wk-1+pz-1z-1z-132 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techniques in PLLsSteepest Descent AlgorithmThe mean square error J(w)=E|e|2 is the typical cost function.The

33、search direction of its global minimum is the opposite direction of the gradient of J(w)(i.e.,along the path of decreasing cost values)The gradient of J(w)depends on the statistics of xk,dkwJ1D case33 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Tec

34、hniques in PLLsConvergence and StabilityConvergence speed depends on step size Stability requires to be positive and limited.The largest the variance of xk,the smallest has to be the step size.wJToo large step size34 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.Levantin

35、oCalibration Techniques in PLLsStochastic Gradient Algorithms:LMS caseStochastic gradient algorithms approximate and track statistical information(learning and tracking mechanism)Case:LMS algorithm uses an instantaneous approximation of statisticsLMS algorithmWidrow and Hoff,1960ekxkFIR filterykdkw1

36、k=w1k-1+xk ekwMk=wMk-1+xk-M+1 ek35 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techniques in PLLsStochastic Gradient Algorithms:LMS caseStochastic gradient algorithms approximate and track statistical information(learning and tracking mechanism)Cas

37、e:LMS algorithm uses an instantaneous approximation of statisticsLMS algorithmWidrow and Hoff,1960ekxkFIR filterykdkw1k=w1k-1+xk ekwMk=wMk-1+xk-M+1 ekApproximates the correlation between xk and ek36 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techn

38、iques in PLLsLMS in the Static(1D)CaseLMS adaptationAdaptive filterComputational cost is 2 multipliers and 2 adders(assuming a power of 2)ekxkykdkw1 k-1w1 k=w1 k-1+xkekekxkykdkw1 k-1z-11-z-137 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceClasses of Adaptive Filter Applica

39、tions Interference cancellation Inverse modeling System identification Linear predictionS.LevantinoCalibration Techniques in PLLs38 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techniques in PLLsInterference Cancellation The desired signal skis corr

40、upted by noise or disturbance nk The filter estimates skbased on nk(that is correlated to nk)AdaptiveFilternknkekskdkSignalestimationObservableSignal corrupted by interferent39 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techniques in PLLsInverse M

41、odelingUnknownSystemDelayAdaptiveFilterekxk The filter becomes the inverse of the unknown system The delay serves to make the system causal Typical application:channel equalization40 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techniques in PLLsSys

42、tem IdentificationekUnknownSystemAdaptiveFilterykykxk The filter mimics the behavior of an unknown system Both system are fed by the same input xk Typical application:channel estimation,echo cancellation41 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibratio

43、n Techniques in PLLsLinear Prediction The filter predicts future values of input signal using past samples Typical applications:predictive coding,line enhancementDelayAdaptiveFilterekxkskykSteady or slowly variable periodic signal42 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits Conf

44、erenceSummaryDigital assistance of analog circuits exploit the low power and high transistor density of scaled CMOS nodesIt enables minimalistic design of analog and mixed-mode circuits,with benefits in power and areaDigital assistance is based on adaptive filters,that allow to:Cancel a noise or dis

45、turbance(interference cancellation)Pre-distort a nonlinear block(inverse modeling)Mimic an unknown system(identification)Predict future values or cancel tones(linear prediction)Adaptive filters can track environmental variations,working in the background of normal operationLMS computation cost is 2

46、multiplier and 2 adders(per each gain)S.LevantinoCalibration Techniques in PLLs43 of 95Calibration ExamplesSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceCalibrations in PLLs:Outline Quantization noise cancellation(Interference cancellation)Automatic bandwidth control(System ide

47、ntification)Linear modulation(Inverse modeling)S.LevantinoCalibration Techniques in PLLs45 of 95Quantization Noise Cancellation in PLLsSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceCancellation of Noise in Digital PLLsS.LevantinoCalibration Techniques in PLLsDisturbance cancell

48、ation is performed at TDC output(digital post-processing)The gain a0that multiplies the quantization error qk is calibrated47 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceCancellation of Noise:LMS loopS.LevantinoCalibration Techniques in PLLsC.-M.Hsu,2008The gain a0conver

49、ges to the value the nulls on average qkekThe adaptive filter estimates the gain of frequency-divider/TDC cascadeek48 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceCancellation of Noise:TDC nonlinearity S.LevantinoCalibration Techniques in PLLsTDC nonlinearity causes imper

50、fect cancellation of quantization noiseThe gain a0converges to a value that minimizes the mean square errorINLa0qe49 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferencePhase Interpolation to Reduce TDC RangeS.LevantinoCalibration Techniques in PLLsNarrowing TDC range reduces it

51、s power and nonlinearity50 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceEffect of PI MismatchesS.LevantinoCalibration Techniques in PLLsThe availability of four phases enable the divider to divide by(N+k/4)Mismatches in the PI phases produces spurious tonesCase of 4-phase

52、 PI51 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMulti-Path LMS Adaptive FilterS.LevantinoCalibration Techniques in PLLsPhase mismatches are corrected by estimating a single hjper each PI phasePhase enable signal52 of 95M.Zanuso,2010SpeakerVideo 2024 IEEE International

53、Solid-State Circuits ConferenceCancellation of Noise:Test ChipdigitalVCOTDCdividerX8XO1.1 mm1.2 mmDACDAC 65nm CMOS Core area:0.4mm2Chip area:1.32mm2 40MHz reference frequency 2.9-4.0-GHz output frequency Power:80mWTDC:24%Divider:63%Absolute jitter:900fs Spurs -57dBcCalibration Techniques in PLLsS.Le

54、vantinoM.Zanuso,201053 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferencePhase Noise at Near-Integer ChannelS.LevantinoCalibration Techniques in PLLs-104 dBc/Hz400kHz10kHz100kHz1MHz10MHzFrequency offset HzPhase Noise dBc/Hz-100-120-140-8030MHz900fs rmsBW=3.27 MHz54 of 95Speake

55、rVideo 2024 IEEE International Solid-State Circuits ConferenceLMS Coefficient ConvergenceS.LevantinoCalibration Techniques in PLLs55 of 95h0,h15SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceOutput Spectrum without/with CalibrationS.LevantinoCalibration Techniques in PLLsTwo mai

56、n fractional spurs in the spectrum(within PLL BW)In-band fractional spurs below-57dBc,with calibration on-39dBc900kHz-40dBc2.12MHz56 of 95-57dBc900kHz-67dBc2.12MHzSpeakerVideo 2024 IEEE International Solid-State Circuits Conference quantization error is cancelled out via a digital/time converter(DTC

57、)The gain a0is calibrated at the input of the DTC(digital pre-processing)S.LevantinoCalibration Techniques in PLLsDTC-Assisted Bang-Bang Digital PLLD.Tasca,2011FCW57 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceCalibration can be done by means of a one-gain LMSS.Levantino

58、Calibration Techniques in PLLsDTC-Assisted Digital PLL:CalibrationCWk1-z-1Cz-158 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceIn a segmented DTC,more gains can be estimated via LMS loopsMulti-path LMS calibration can replace the one-gain LMS to correct for DTC nonlinearit

59、yS.LevantinoCalibration Techniques in PLLsDTC-Assisted Bang-Bang Digital PLL59 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceCancellation of Quantization Noise:Test Chip 65nm CMOS Core area:0.52mm2Chip area:1.00mm2 40MHz reference frequency 2.9-4.0-GHz output frequency Pow

60、er:4.2mW Absolute jitter=502 fs Spurs -52dBc Multi-Path LMS with 16 coefficientsCalibration Techniques in PLLsS.LevantinoS.Levantino,201460 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceS.LevantinoCalibration Techniques in PLLsMeasured Spectral PurityIn-band fractional lev

61、el of-52dBc at about 50kHz61 of 95Absolute Jitter=502 fsDTC calibrationPhase Noise dBc/Hz Offset frequency HzSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMany different implementations of DTC-assisted digital PLLs have been presented in recent literatureS.LevantinoCalibration

62、Techniques in PLLsModern DTC-Assisted Digital PLLsrefdivfcwmckekBPDDTCLoopFilterMulti-ModulusDividergkAccC62 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceDTC assistance with LMS has been extended to analog PLLsSampling phase detector(SPD)reduces noise impact of subsequent

63、 blocksS.LevantinoCalibration Techniques in PLLsDTC-Assisted Sampling PLLMulti-ModulusDividerLoopFilterGmVCOoutSPDdivCoarse TuningreffcwmckDTCgkAccC63 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferencePLL Jitter-Power Figure of Merit In PLLs,jitter variance scales as power con

64、sumption Thus,a figure of merit(FoM)defined as Jitter2x Power is used to compare different designs DTC-assisted PLLs(red dots)have on average 10dB better FoM than traditional PLLs(blue dots)Calibration Techniques in PLLsS.Levantino64 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits Con

65、ferenceState-of-the-art Performance of PLLs Jitter of integer-N PLLs is typically lower than fractional-N because of residual quantization noise Record jitter of 20.3fs achieved in a 19GHz integer-N PLL Zhao,2021 Record jitter of 58.2fs achieved in a 12.5GHz fractional-N PLL Mercandelli,2020Calibrat

66、ion Techniques in PLLsS.Levantino65 of 95Automatic Bandwidth Control in PLLsSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLoop Gain SensitivityS.LevantinoCalibration Techniques in PLLstrefktkKbbtoutk-ektqkF(z)Loop FilterDCOKTv1-z-1z-1PLL Linear modelOpen-loop gain depends on th

67、e jitter through the BPD gainBoth BPD and VCO gains are sensitive to PVT spreads67 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLoop Gain and Transfer FunctionS.LevantinoCalibration Techniques in PLLsOpen-loop gain depends on the jitter through the BPD gainSystem BW is al

68、so sensitive to jitter and PVT spreads|LG|f|T|f|LG|f|T|f|BW68 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLoop Gain Normalization:Problem DefinitionS.LevantinoCalibration Techniques in PLLsTransfer function from DCO tuning wk to error ek is proportional to GTraining sequ

69、ence qk is injected into DCO tuning wkqkekwkG z-11-z-1tk-1wkKbbekF(z)Loop FilterDCOKTdco1-z-1z-1G“Unknown”system69 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLoop Gain Normalization:Working PrincipleS.LevantinoCalibration Techniques in PLLsThe digital integrator with ad

70、aptive gain gk mimics the loop behaviorThe LMS sets gk such that k k is nulled qkekekwkgkz-11-z-1CG z-11-z-1G.Marzin,2014Adaptive FilterUnknown System70 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferencePLL with Automatic BW Control(ABWC)S.LevantinoCalibration Techniques in PL

71、Ls-DCO quantization noise qk trains the adaptive filterAs the loop error ek is divided by the estimated gain gk,the open-loop gain is now independent on analog parameters1-z-1Cgk GOn average:refoutdivekwkgkBPDLoopFilterAccInvCMulti-ModulusDividerAdaptive Filter k z-171 of 95SpeakerVideo 2024 IEEE In

72、ternational Solid-State Circuits ConferencePhase Noise Profile vs.DCO gainS.LevantinoCalibration Techniques in PLLsSensitivity of PN to DCO gain variations is cancelled outDCOgainPhase Noise dBc/HzFrequency Offset HzFrequency Offset HzDCOgainMulti-tap Adaptive FilterNo Adaptive Filter72 of 95Speaker

73、Video 2024 IEEE International Solid-State Circuits ConferencePhase Noise Profile vs.Input Noise LevelS.LevantinoCalibration Techniques in PLLsBW of PN profile is made insensitive to variations of input-noise levelMulti-tap Adaptive FilterNo Adaptive FilterPhase Noise dBc/HzFrequency Offset HzFrequen

74、cy Offset Hzinput noiseinput noise73 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLoop Gain Normalization:Test ChipCalibration Techniques in PLLsS.Levantino 65nm CMOS Active area:0.61mm2 52MHz reference 3.7-to-4.1GHz output Power:5.3mW Absolute jitter:183fs PLL BW:150kHz

75、16-tap ABWCM.Mercandelli,202174 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLoop Gain Normalization:Measurements(1/2)Voltage supply varied from 0.9 to 1.2V Loop gain normalization maintains the same loop BWCalibration Techniques in PLLsS.LevantinoSupply 1.2VABWC OnSupply

76、 0.9VABWC On(a)(b)Supply 0.9VABWC OffLow NoiseABWC OnHigh NoiseABWC OnHigh NoiseABWC Off75 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLoop Gain Normalization:Measurements(2/2)Input phase noise from-110 to-100 dBc/Hz(ref.to fout)Loop gain normalization maintains same loo

77、p BWCalibration Techniques in PLLsS.LevantinoSupply 1.2VABWC OnSupply 0.9VABWC On(a)(b)Supply 0.9VABWC OffLow NoiseABWC OnHigh NoiseABWC OnHigh NoiseABWC Off76 of 95Linearized FM Modulation of a PLLSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceDirect FM Modulation Pro:low power

78、 consumption,fine resolution,linearity Cons:slow frequency switching,fractional spursS.LevantinoCalibration Techniques in PLLsdivekoutrefLoopFilterTDCModulusControlFrequencyDividerDCODS-nkModulation rate limited by loop BW78 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceTw

79、o-Point Injection Enables fast direct-FM modulation of a PLL Requires gain calibrationS.LevantinoCalibration Techniques in PLLsAll-pass transfer function if the two gains matchdivekoutrefLoopFilterTDCModulusControlFrequencyDividerDSg0-nknkDCO79 of 95SpeakerVideo 2024 IEEE International Solid-State C

80、ircuits ConferenceTwo-Point Injection:Mathematical ModelS.LevantinoCalibration Techniques in PLLse z()=n z()2pfref-g0KdcoGloopz()1+Gloopz()1KdcoH z()F z()80 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceTwo-Point Injection:Gain ImbalanceS.LevantinoCalibration Techniques in

81、 PLLsCorrelation ck=E eknk is proportional to gain imbalance KF(z)divekoutrefLoopFilterTDCModulusControlFrequencyDividerDSg0-nknkDCOK81 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceTwo-Point Injection:Gain CalibrationS.LevantinoCalibration Techniques in PLLsThe LMS loop n

82、ulls k,thus nulling the gain imbalance KdivekoutrefLoopFilterTDCModulusControlN/(N+1)DividerDCO-nknk g0nkckg01-z-11-z-1z-182 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceTwo-Point Injection:DCO NonlinearityS.LevantinoCalibration Techniques in PLLsDCO gain differs at the e

83、dges of tuning rangeIntra-bank nonlinearity from capacitor mismatchesChirp modulation would contain frequency errors0FrequencyError0TimetwTimefout0Kdco,maxKdco,minffoutpCK CoutnK CC83 of 95Chirp ModulationDCO Tuning CurveSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceFrequency E

84、rror Induced by NonlinearityS.LevantinoCalibration Techniques in PLLs1-z-1Ktdc1N-n(z)H(z)g0 n(z)(1+K)2pN 1-z-1KdcoTref1-z-12pTreffout(z)1e(z)out(z)ref(z)Modulation leakingGain imbalance Kcauses modulation leaking into the loop84 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits Conferen

85、ceImpact of DCO NonlinearityPLL can correct for gain imbalance only if modulation is within PLL BWOut-of-band frequency error are not corrected by the loopS.LevantinoCalibration Techniques in PLLsnk frefnk fref+feknk g0Kdco(1+K)2pfref(1+K)(1+K)f0f0f011DCO pathDIV pathTwo-Point85 of 95SpeakerVideo 20

86、24 IEEE International Solid-State Circuits ConferenceSolution:Adaptive DPD AlgorithmS.LevantinoCalibration Techniques in PLLsdivektwkoutrefLoopFilterTDCModulusControlN/(N+1)Divider-nkDCOtwfoutKdco,maxKdco,min1-z-1qck1g0g1nkqfkqfkc010101010c1twg1c0c1ng0Piecewise inverse functionTwo-slope calibration

87、case(for simplicity)D.Cherniak,201886 of 95S.Levantino,2014SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceSimulation of Adaptive DPDS.LevantinoCalibration Techniques in PLLsDPD mitigates the negative impact of DCO INL and intra-bank mismatch20.019.520.5Time s-10010Two-point w/o

88、DPDTwo-point w/o DPDTwo-point w/DPDTwo-point w/DPDFrequency GHz Error%-0.2-0.100.10.2Error%Time s02002002087 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLinear Chirp Generator:Test ChipS.LevantinoCalibration Techniques in PLLs 65nm LP CMOS(no UT top metal)Active area:0.4

89、8mm2 52MHz reference frequency 20.4-to-24.6GHz output frequency Power:19.7mW Absolute jitter:242fs Spurs -58dBc88 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMeasured Phase NoiseS.LevantinoCalibration Techniques in PLLsPhase noise at 1MHz:-112dBc/Hz(at 5GHz)or-100dBc/Hz(

90、at 20GHz)Fractional-N(J=242fs)Integer-N(J=213fs)89 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMeasured Frequency Modulation and ErrorS.LevantinoCalibration Techniques in PLLsChirp slope up to 173MHz/s with 0.06%frequency error and 200ns idle timeTC=10sTC=1.2sTidle=0.2s5

91、2MHz x 4=208MHz90 of 950.06%RMS714kHz repetition rate100kHz repetition rateSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMeasured Frequency JumpS.LevantinoCalibration Techniques in PLLsFast frequency switchingTurn-around time is 2.4ns TC=10s0.06%RMS52MHz x 4=208MHz2.4ns91 of 95

92、SpeakerVideo 2024 IEEE International Solid-State Circuits ConferencePapers to See This YearSession 10 Relevant Papers:10.1:Digital PLL with reverse-concavity variable-slope DTC10.2:Digital PLL with recursive-least-squares(RLS)algorithm10.5:Sampling PLL with nonlinearity-replication technique10.6:Chi

93、rp modulator with non-uniform piecewise-parabolic predistortion10.7:Chirp modulator with second-order digital predistortion S.LevantinoCalibration Techniques in PLLs92 of 95SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceConclusionsDigital assistance of analog circuits enables mi

94、nimalistic design of analog and exploits transistor scalingDigital assistance is based on adaptive filters that have the ability to learn from the behavior of the system and track environmental variationsPhase locked loops benefit from the adoption of adaptive filters,that enabled the introduction o

95、f DTC-based analog and digital architectures(has improved the jitter-power FoM of PLLs)Examples of adoption of adaptive filters have been shown:Cancellation of fractional quantization noiseAutomatic bandwidth regulationLinearized FM modulation of a PLLS.LevantinoCalibration Techniques in PLLs93 of 9

96、5SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceKey References(1 of 2)B.Murmann,B.E.Boser,“Digitally assisted analog integrated circuits,”ACM Queue,vol.1,Mar.2004.B.Murmann,“Digitally Assisted Analog Circuits,”IEEE Micro,vol.26,no.2,Mar.2006.G.C.Gillette,“Digiphase Synthesizer,”

97、in Proc.of 23rd Annual Symposium on Frequency Control,May 1969.T.A.D.Riley,M.A.Copeland,T.A.Kwasniewski,“Delta-sigma modulation in fractional-N frequency synthesis,”IEEE J.of Solid-State Circuits,vol.28,May 1993.Dana Series 7000 Digiphase Frequency Synthesizers(7010-S-241),Pubblication 980428,Dana L

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