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10-Semidynamics-RISCV-Summit-China-Atrevido.pdf

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10-Semidynamics-RISCV-Summit-China-Atrevido.pdf

1、Tailor-Made High Performance RISCV64 IPIn OrderCoreOOO CoreOOO Vector UnitAbout SemidynamicsSemidynamics is a European supplier of RISC-V IP cores,specializing in customization of high bandwidth high performance cores with vector units for tailored projectsExperts in open core surgeryBarcelonaSan Jo

2、se CAShenzhenSeoulOur RISC-V Core IP FamiliesAtrevido2,3 or 4-wide out-of-orderRISCV64GCV AXI and CHIAvispado2-wide in-orderRISCV64GCV AXI and CHIWorlds first,fully customizable,64-bit RISC-V cores for ultra fast,big memory applications,optimized for a companion RISC-V vector unitUnique tailor-made

3、PPA solutions include customers secret sauce for product differentiation and IP protection.Whats special about our RISC-V Cores?We fully customize each core to the customers precise application needsWe can include unique customer features in a few weeksFastest cores on the market for moving big data

4、Gazzillion turbo-charges memory retrievalProcess agnostic already done 5nmSupport for OOO RISC-V Vector UnitAvispado 22364b RISC-V CoreMid-Range Performance In-order executionUser,Supervisor and Machine privilege levelsHypervisor available Q4Linux-Ready memory subsystemMemory Management Unit(MMU)Sup

5、ports SV39/48/57Coherent caches with ECC,ParityHardware support for unaligned accessesHardware support for AtomicsPMP Regions(0 to 16)AXI4 or AMBA CHI.B compliant interfaceAdvanced Debug CapabilitiesRISC-V debug spec compliant interface over JTAGHW/SW Breakpoint supportRISC-V Extensions supported:Ve

6、ctor,Crypto,Bit Manipulation,CMOs,ZifenceiQuad-Core ReadyAvispado 223I-TLBInstruction Cache(4,8,16 or 32KB)DecoderTAGERASBTBDebugALUALUFPUAGUInteger RegsFP RegsD-TLBData Cache(4,8,16 or 32KB)ECCPMUGazzillion UnitMMUSV39/48/57AXI/CHIPARCRYPTO512b8BPMPAXI/CHIAtrevido 32364b RISC-V CoreHigh-End Perform

7、ance Out-of-order execution3-wide decode,rename,retireUser,Supervisor and Machine privilege levelsHypervisor available Q4Linux-Ready memory subsystemMemory Management Unit(MMU)Supports SV39/48/57Coherent caches with ECC,ParityHardware support for unaligned accessesHardware support for AtomicsPMP Reg

8、ions(0 to 16)AXI4 or AMBA CHI.B compliant interfaceAdvanced Debug CapabilitiesRISC-V debug spec compliant interface over JTAGHW/SW Breakpoint supportRISC-V Extensions supported:Vector,Crypto,Bit Manipulation,CMOs,ZifenceiQuad-Core ReadyAtrevido 323I-TLBInstruction Cache(4,8,16 or 32KB)DecoderTAGERAS

9、BTBDebugAGUInteger RegsFPUFP RegsALUD-TLBData Cache(4,8,16 or 32KB)ECCPMUGazzillion UnitMMUSV39/48/57PARALUCRYPTO512b/1024b16BBRPMPMem Issue QueueInt Issue QueueFP Issue QueueRenamerBR Issue QueueAXI/CHIAtrevido 42364b RISC-V CoreHigh-End Performance Out-of-order execution4-wide decode,rename,retire

10、User,Supervisor and Machine privilege levelsHypervisor available Q4Linux-Ready memory subsystemMemory Management Unit(MMU)Supports SV39/48/57Coherent caches with ECC,ParityHardware support for unaligned accessesHardware support for AtomicsPMP Regions(0 to 16)AXI4 or AMBA CHI.B compliant interfaceAdv

11、anced Debug CapabilitiesRISC-V debug spec compliant interface over JTAGHW/SW Breakpoint supportRISC-V Extensions supported:Vector,Crypto,Bit Manipulation,CMOs,ZifenceiQuad-Core ReadyAtrevido 423I-TLBInstruction Cache(4,8,16 or 32KB)DecoderTAGERASBTBDebugAGUInteger RegsFPUFP RegsALUD-TLBData Cache(4,

12、8,16 or 32KB)ECCPMUGazzillion UnitMMUSV39/48/57PARALUCRYPTO16BBRPMPMem Issue QueueInt Issue QueueFP Issue QueueRenamerBR Issue Queue512b/1024bAtrevido 423+V8 Vector UnitAXI/CHIAtrevido 423-V8I-TLBInstruction Cache(4,8,16 or 32KB)DecoderTAGERASBTBDebugAGUInteger RegsFPUFP RegsALUD-TLBData Cache(4,8,1

13、6 or 32KB)ECCPMUGazzillion UnitMMUSV39/48/57PARALUCRYPTO512b/1024b16BBRPMPMem Issue QueueInt Issue QueueVector,FP Issue QueueRenamerBR Issue QueueVector RegsVcoreVcoreVcoreVcoreVcoreVcoreVcoreVcoreVector UnitVle(x5)-v4Vle(x6)-v5Vfma v4,v5,v1 v6Vsqrt v6 v6Vse v6 (x7)Atrevido 423+V16 Vector UnitAXI/CH

14、IAtrevido 423-V8I-TLBInstruction Cache(4,8,16 or 32KB)DecoderTAGERASBTBDebugAGUInteger RegsFPUFP RegsALUD-TLBData Cache(4,8,16 or 32KB)ECCPMUGazzillion UnitMMUSV39/48/57PARALUCRYPTO512b/1024b16BBRPMPMem Issue QueueInt Issue QueueVector,FP Issue QueueRenamerBR Issue QueueVector RegsVcoreVcoreVcoreVco

15、reVcoreVcoreVcoreVcoreVector UnitVcoreVcoreVcoreVcoreVcoreVcoreVcoreVcoreVle(x5)-v4Vle(x6)-v5Vfma v4,v5,v1 v6Vsqrt v6 v6Vse v6 (x7)Gazzillion TechnologySERIALTraditional method of memory retrieval is stop and go.Request some piece of data from memory and wait doing nothing over several hundred clock

16、 cycles for it to come back.PARALLELGazzillionTMsends out up to 128 simultaneous requests for data from memory.Whichever data request comes back first is worked on and then the next one back so that core is always working.128 of these streams in parallel bringing data back to the core really turbo c

17、harges performance.Turbo charges memory retrievalTolerates memory latency like no otherGazzillion compared to other CPUs123456Retirement/Issue Width20406080100120140POWER9 SMT41612IceLake64+Avispado128+AtrevidoA7620RISC-V Boom10Outstanding MissesU8SCR7AX25Vector+Gazzillion:A bandwidth rocket!Can you

18、 find a core out there capable of streaming data at over 60 Bytes/cycle?And from main DDR memory(not from your cache)?We dont think so READWRITE8 vector cores,32X vector lengthBytes/CycleArray SizeL1 CacheL2 CacheDDRDGEMM on Atrevido 423+V8(FP64 matrix multiply)Vector Unit with 8 vector coresPeak of

19、 16 FP64 flops/cycle99%of peak for M=40050%of peak(N)for M=24 50%100%Matrix Size MxMFLOPS/cycleYolo on Atrevido 423+V8YOLOv3-tiny:24 layers,5.56 Gops/frame,9M paramsUsing SGEMM(FP32)for Matrix MultiplicationPlatform Vector/CudaCoresFrequency(Ghz)FPSFPS per 8 vector cores 1GhzJetson TX22561.301910.46

20、Jetson AGX Xavier5121.383210.36GTX Titan X30721.0922020.53Atrevido 423-V881.000.840.841 https:/ Board_Deep_Learning_Fault_Detection_for_Autonomous_UAV_Inspections2 https:/ performance per vector coreFlexible and customizable Business ModelCustomize IPAXI,CHICache SizesBranch predictorCustom instructionsRV32Small CoreEvaluateSingle CoreMulti CoreVector UnitLicenseLicense FeeRoyaltiesMaintenanceBug FixesTiming fixesArea FixesTHANK YOU!

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