1、晶心持续协助RISC-V 于科技领域领先全球林志明晶心科技董事长暨执行长&RVI董事2Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologyN25F,N45MobileAndes RISC-V Powering Rich ApplicationsEndpoints.Edge.Cloud.Space.D25F,D45,AX25MP,AX45MPN25F,N45,AX45MPN25F,A25,A45MP,AX45MPN25FSpaceSecure,control,compute,co

2、mmunicate,positionNX27V,AX25,AX27,AX45MP,AX45MPVCloud AIAccelerate,accelerate,accelerate3Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologyAIOTn Renesas Voice-Control ASSP Solutionn R9A06G150 32-bit 100MHz ASSP with Andes DSP-capable D25F,which speeds up the applic

3、ation by over 50%.n Cyberon,an expert in voice recognition technologyn Orbstar,a system integrator specializing in embedded solutionsn SEGGER,supporting the ASSP with Embedded Studio and J-Linkn ASUS IoT Tinker V Single-Board Computer:n Based on Renesas RZ/Five 1 GHz SoC with Andes AX45MP n Supporti

4、ng Linux Debian and Yocto distro with rich connectivityn Ideal for Industrial IoT and gateway applicationsPowered by Andes D25F/AX45MP4Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologynPhison X1(PS5020-E20)Enterprise Storage lLeveraging N25F with Andes Custom Exte

5、nsion“The ACE automation tool is very powerful in creating customized instructions that fits our exact needs”,Vincent Cheng,VP of R&D of PhisonlFor AI,HPC,and Hyperscale DatacentersEnterprise Storage and Spherical Image ProcessornAspeed AST1230 Multi-Cam PanoramaImage ProcessorlUsing N25F for 8K2K r

6、eal-time 360ocameras with rich audio processinglFor immersive applications such as video conferencing,virtual factory inspection/audit,shopping,touring,house showing,etc.Powered by Andes N25F and ACE5Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologyPicocom PC80 x

7、uses RISC-V Clusters and Linux corenLow powernFlexible control forlTask schedulinglMemory managementlEvent handlingnComputation assistance forlDFE(Digital Frontend)lDPD(Digital Pre-Distortion)nSupport protocol/interface upgradeslCPRI(common public radio interface)leCPRI(enhanced CPRI)nFriendly devel

8、opment environment:lZephyr and Linux for application development5G Small Cell SoC for Open-RANPowered by Andes N25F/A276Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologySoCIPUClusterAI Accelerator Using Compute-in-MemoryIPUTileArrayBus NodeLDSTPre/Post Processingn

9、 Houmo H30 CIM SoCn CIM Macros provide 256 TOPs(int8)in an H30n NX27V Vector processor:Flexibility to tackle Long Taill Each provides 128 GOPS thru versatile RVVl ACE tools greatly simplify custom instruction extensionsTileShared Memory&ControllerNX27VScalar UnitSFUVPTEMacro ArrayVector UnitAndes St

10、reaming Port(ASP)Powered by Andes NX27V+ACESRAM-CIM Macro7Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologyAI Accelerator Using Analog In-Memory-Computen TetraMem Analog In-Memory-Compute MX200n 8-bit 256x256 MAC Engine,30 TOPS/W performance n AI Core operators(co

11、nv,gemm)processed in NPUn Remaining operations processed in Vector Engine and CPUTCDM(Tightly Coupled Data Memory)Bus SRAM Bank0CPU Core with vector engine Logic Banks of NN SRAM AXI BusI$D$ILMDirect Stream PortSRAM Bank1SRAM Bank NStream port to TCDM Maser7AXI2 AHB BridgeMultiple NPU cores share on

12、e TCMD master port NPU cores Access Agent AXI2 TCDM Master 8AHB BusDLMNPUNPUUARTSPII2CJTAGGPIOI2SOthersPowered by 8 bits multi-level RRAM deviceBottom ElectrodeSwitching OxidesTop ElectrodeInterfacial Layer The physical deviceThousands of conductance levels in memristors monolithically integrated on

13、 CMOS”led by TetraMem,Nature,Mar 2023,https:/rdcu.be/c8GWoPowered by Andes NX27V+ACE8Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologynISCA 2023 paper,“MTIA:First Generation Silicon Targeting Metas Recommendation Systems”nProc-A/B:Andes AX25-V100,an early version

14、of the popular NX27VnCustom extensions:for new interfaces,instructions and registersnPerforms quite well on low and medium complexity modelsMTIA:Meta Training and Inference AcceleratorPowered by Andes NX27V+ACEAll photos:courtesy of ACM9Taking MainstreamSubject to change without noticecopyright 2021

15、-2023 Andes Technologyl13-stage 4-way 64-bit OOO processorlRVA22+profilelMulticore cluster up to 8 coresl8 Execution Pipes:4 ALU,2 LD/ST,2 FPl2-Level BTB with TAGE-L Branch PredictorlCaches:Private I/D caches:64 KB,4-way,4-bank Shared cache:up to 8 MB,16-wayl256-bit AXI4 for Memory,MMIO and IOCPlPer

16、formance:2.4 GHz*7nm without overdrive Specint2006:8.25/GHz Specfp2006:10.2/GHzAndesCore AX65 OOO Application ProcessorBest spec2k6 with 2-level cachesMemoryIRQsAndesCore AX65Trace PortsAX65corePrivate$AX65corePrivate$.Debug SupportInterrupt ControllerJTAGMMIOShared CacheCoherence Manager(CM)Coheren

17、tIO07*Typical caseB1F1F2D1 D2D3I1I2E1E2E3E4issue,register readALU WB x3batch,fetch,align&bufferdecode,rename,dispatch+br&miscWB x1m e m o r yWB x2floating pointWB x210Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologyRoadmap for the AX60 SeriesEfficientMid-rangeExt

18、endedAX60 Series:13-stage OOO Linux MPAX63Power-optimizedAX65BalancedAX66Multi-clusterAX67RVA24 andmost performant11Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologyAX45MPV Multicore ClusterSPPnAt multicore cluster level:lUp to 8 coreslCM/L2$subsystem 128KB to 8MB

19、,64B line,16-way Multi-cycle support for high-density SRAMs I/D prefetch,up to 64 outstanding requestslAXI Bus Interfaces up to 512 bitsnScalar Unit:RV64GCBPl8-stage In-order dual-issuelMMU/SV48,M/S/U modeslI/D caches:8K64KB;Parity(I$)or ECC(both)nRISC-V Vector Extension(RVV v1.0)ldata format:int864

20、,fp1664;int4,bf16lVLEN/DLEN:1281024 bits,1:1 or 2:1 ratiolUp to 6 DLEN results per cycle12Taking MainstreamAX45MPV:1024-bit Vector ProcessornRISC-V Vector Extension(RVV v1.0)ldata format:int864,fp1664;int4,bf16lVLEN/DLEN:1281024 bits,1:1 or 2:1 ratiolUp to 6 DLEN results per cyclenEfficient support

21、needed for tight coupling with HWE1.Data exchange performance(from/to shared memory in HWE)2.Efficient control to the HWEn2 solutions offered in AX45MPV:lAndes Streaming Port(ASP)thru ACE Data bus:data transfer btw VR and HWE Command bus:to control/synchronize HWE operationslHVM:High-speed Vector Me

22、mory CPU side:DLEN-wide load/store interface with dynamic wait cycles HVM module:accepting multiple accesses to multi-bank SRAMslBoth can be used at the same time to achieve 2x DLEN/cycle bandwidth into VRFF1F2IDIIEXMMLXWBAndes Vector CoreHardwiredEngine(HWE)Processing Element(PE)V P UASPScalarMemor

23、y Subsys.HVM13Taking MainstreamSubject to change without noticecopyright 2021-2023 Andes TechnologyAndes Custom Extension for AX45MPVnACE:Create new instructions to speed up computations and controlsnExtend it to support RVV-style instructionsCPU RTLExtensible Baseline ComponentsCompilerAsm/DisasmDe

24、buggerIDEExtendedToolsExtendedISSC O P I L O TC semanticConcise VerilogAttributes-custom registers,memory,ports-arbitrary width and numberExtendedRTLSimulatorSC with near-cycle accuracy,Qemu,Imperas14Taking RISC-VMainstreamnSupporting a Wide Variety of Functional Safety Applications:lDashboard displ

25、ay,in-car monitoring,keyless entry,lighting control,tire pressure monitoring,vision ADAS,microcontroller and many morenDevelopers using AndesCore Functional Safety Processors to:lIntroduce new electronic systems on automobileslUpgrade existing systems that needs to be ISO 26262 compliantAndesCore fo

26、r Automotive ElectronicsHead LightsIn-car MonitoringTouch&DisplayBlind Spot MonitorEPSBMSESCSensors&ActuatorsKeyless Control15Taking RISC-VMainstreamAndesCore RISC-V Functional Safety RoadmapMainstream ProcessingHigh PerformanceLow Power&SecurityComputing PowerD25F-SE5-stageSingle-issueN25F-SE5-stag

27、eSingle-issueASIL-B CompliantIP:Available nowAlready CertifiedLegendReleasedDevelopingPlanningASIL-B CompliantIP:June 2023Certified:Q3,202360-Series13-stage,OoO4-issueASIL-D Compliant(planning)D45-SE8-stageDual-issueD23-SE3-stageSingle-issue202320242025 Mission CriticalASIL-D CompliantASIL-B Support

28、edIP:Q4,2023Certified:Q3,2024 ASIL-D CompliantASIL-B SupportedIP:Q2,2024Certified:Q4,202416Taking RISC-VMainstreamnCPU Corel5-stage,in-order,single-issue architecturelRISC-V RV32 GCBP*ISA,with Andes Extensions D25F-SE with the RVP(SIMD/DSP)instruction extension RVB bit-manipulation instructions for

29、cryptography,applicationslAndeStar V5 32-bit architecturenMemory SubsystemlInstruction and data caches,up to 32KB eachlInstruction and data local memories,up to 16MB eachnBus Interfaces and System IntegrationlAXI or AHB bus master portlLocal memory direct access portnFunctional SafetylCore trap stat

30、us bus interface,lECC protection,StackSafe,PMP lN25F-SE,ASIL-B certified.D25F-SE,ASIL-B certified at Q3/2023N25F-SE,D25F-SE 5-Stage,ASIL-B Full Compliant17Taking RISC-VMainstreamn“The product has been approved in compliance with ASIL B requirements”nISO 26262 Edition 2018,parts:lISO 26262-2:2018lISO

31、 26262-4:2018*lISO 26262-5:2018lISO 26262-8:2018lISO 26262-9:2018nCertification BodylSGS-TV Saar GmbHlSGS-TV Saar GmbH accredited by German accreditation body DAkkS*Part-4 System/item level integration,validation is not applicable to CPU IPAndesCore N25F-SE Certified by ISO 2626218Taking RISC-VMains

32、treamnCPU Corel8-stage,in-order,superscalar,dual-issue most instruction pairslRISC-V RV32 GCBP*support,Andes ExtensionslAndeStar V5 32-bit architecturenMemory SubsystemlInstruction and data cache,up to 64KBlInstruction and data local memory,up to 16MBlMemBoostnAXI Bus InterfaceslSystem port,and flas

33、h port(64/128-bit)lLM access port(64/128-bit)lPrivate,and shared peripheral interface(64-bit)nFunctional SafetylLockstep and Split mechanismlConfigurable ECC for every memorylCore trap status bus interfacelBus protection,StackSafelCertified estimated by or before Q3/2024*P:draftD45-SE 8-Stage,Dual-I

34、ssue,up to ASIL-D19Taking RISC-VMainstreamD23:Compact Controller for IoT/MCU/ECUn3-stage,limited dual-issue(optional)nISA extensions:lBase:RV32 I/E-MAC+B+ZcelAdvanced:FD+P+K+CMOnPrivilege modes:M,S,UnConfigurable featureslBranch prediction:none,static,dynamiclMultiplier options:Sequential:1/2/4/8-bi

35、t per cycleFast:pipelinedlAndes Custom Extension(ACE)lPower management:WFI/WFE,PowerBrakelCore-Local Interrupt Controller(CLIC)1000 sources,255 priority levelsSelective vectoring with priority preemptionP:draft3-stage uCore,ePMP/sPMP/PMAWFI/WFEDebug&Trace I/FCLICBr.PredAHB-LI$Debug TracePMULM Access

36、PortDLMD$FPUDSPACE1000InterruptsAPBAHB-LMult/DividerAHB-LSystem PortPeripheral PortLow latency PortILMTimer20Taking RISC-VMainstreamD23:Compact Controller for IoT/MCU/ECUnMemory subsystem:l Caches:Config:Icache only:ifetchRO-cache(Read-Only):ifetch and loadI/D caches:ifetch,load and store Cache size

37、s:1KB32KB Error protection:ECC for I$and D$l I/D Local Memory(LM):0512MB with ECC Interface:SRAM or AHB-LnD23-SE Safety-Enhanced D23 for Automotive designs,ASIL-D compliant&ASIL-B supportedRISC-V Code Size BenchmarksISAIMACIMAC+V5(N22)IMABC+V5(N25F)IMABZce+V5(D23)SPEC CPU2,840 2,360-16.9%2,346-17.4%

38、2,247 20.9%CSiBE1,462 1,204-17.6%1,190-18.6%1,144 21.8%Audio Codec842 682-19.0%671-20.3%656 22.1%Embench-IoT63.6 51.2-19.5%48.9-23.1%48.4 23.9%21Taking RISC-VMainstreamSecurity System Architecture for D23(D23-SE)Create multiple zones protection by PMP/sPMPREEs(Rich Execution Environment)TEEs(Trusted

39、 Execution Environment)IOPMP for IO protection PMP,ePMPAndes RISC-V Cores ie D23(D23-SE)InterconnectSoCHWPeripheralsMemoryCrypto EngineDSPTraceDebugPMP,sPMPRoot of TrustIOPMPIOPMPREETEEFuSaEESecure MonitorSecure BootHardwareMachine ModeSupervisor ModeIOPMPIOPMP22Taking RISC-VMainstreamnCo-working wi

40、th global leading suppliers in the automotive industrylAndes and ecosystem partners jointly deliver the trusted RISC-V automotive solutions to designers complying with the standard of functional safety ISO 26262nAndes Ecosystem PartnersThe Andes Automotive EcosystemCapital VSTARNucleus SafetyCertLDR

41、A Tool SuiteParasoft C/C+TestVOSySmonitoRVRiscFree IDE/CompilerMULTI IDE/Compiler RTOSAUTOSARMicrosoft Azure RTOSMaaZ AUTOSARSAFERTOSVxWorksCompilerHSM/RoTCompiler/Debugger/ToolAUTOSARSafety RTOSTRACE32 DebuggerSecuritySecuryzr SETEEEWRISCVTaking RISC-VMainstream23Subject to change without noticecop

42、yright 2021-2023 Andes TechnologyAndesAIREAnDLAI350The First Generation of Andes Deep Learning AcceleratorAndesAIRENN SDKUnleash the maximum AI/ML performanceand synergy of RISC-V CPU and AnDLA24Taking RISC-VMainstreamAndesAIRE AnDLA I350Andes Deep Learning Accelerator(AnDLA)High performance-efficie

43、nt deep learning accelerator for edge and end-point inferenceScalable and multi-DLACooperate with AndesCorefull series(22/23/25/27/45/65)Accelerating for most of NN ApplicationsImage and videoSpeech/voice and audioTarget performanceConfigurable MACs:32 to 4096(INT8)Performance:64 GOPS to 8 TOPS(INT8

44、 1GHz)Configurable local memory:16KB to 4MBLeading power efficiency 5 TOPS/W(28nm)Integrated DMA and local memoryGeneral Matrix MultiplySystem BusAnDLAI350Convolution AccumulatorElement-Wise Data ProcessingPooling Feature ProcessingDMALocalMemoryAndesCoreCustomBPV25Taking RISC-VMainstreamnMore NN mo

45、dels and operators supported from RISC-V DSP/SIMD and Vector processornCPU plays the key role oflThe fallbacks of non-structural operators(not good to hardwired)such as non-linear functionslThe flexibility to create extensible and future-proof AI/ML applicationsAccelerating for Most of NN Models and

46、 OperatorsNN ModelsOperatorsImage and video AlexNet VGG-16/19 Mobilenet-v1/v2/v3 ResNet-8/50 Tiny YOLO v1/v2 YOLO v1/v2/v3/v4/v5 SSD MobileNet v1/v2 Inception v2 EfficientNet-lite MobileFaceNet BlazeNetSpeech/Voice and audio LSTM RNN GRU Conv2d,depthwise conv,pointwise conv,transpose conv,dilated co

47、nvolution Element-wise(add,sub,mul)Fully connected Activation(ReLU,leaky ReLU,sigmoid,Tanh,ReLU6,SiLU)Pooling(max,ave)Upsample Concatenation Batch normalization Channel padding Operator fusion:GEMM+GEMM,EDP+EDP,GEMM+EDP26Taking RISC-VMainstreamAndes AI Total SolutionsBusNN inference enginesNN models

48、AndesAIRE NNPilotGenerated C code templateAndesAIRENN SDKAndesAIRE NN LibraryAndeSoft Vector/DSP LibraryAnDLA driverLinux Host ProcessorAX45MP(V),AX65Compute AccelerationVector:27V,45VDSP/SIMD:D25F,D45AcceleratorAnDLA I350AndeSightIDE GCC/LLVM Toolchains Build,debug,deploy,profile Analysis and tuning RTOS&Linux Device drivers Sample codes Simulator Documentation27Taking RISC-VMainstreamAndesAIRE-Andes AI Runs EverywhereSmart CameraSmart Home ApplianceSmart SensorAIoT/tinyMLRoboticsWearableThank You!