1、RISC-V with HW/SW co-design and Custom Compute Author:Julian HURISC-V Summit China 20232 2023 Codasip.All rights reserved.Challenge in the market Need to optimize processing to the application Custom ComputeDifficult and risky to do by handUsually takes too longUsually is not optimalRequires large t

2、eamsNo more“free improvements”with end of Moores law3 2023 Codasip.All rights reserved.Benefits of Custom ComputeReduce powerReduce areaFor example,remove companion DSP,compress codeBeat the competitionProtect against copyYour custom processor is uniqueUse older nodesPush boundariesImprove performan

3、ceImprove efficiencyDifferentiate4 2023 Codasip.All rights reserved.Leaders use Custom ComputeVery long and difficultUnderstand the application needsDesign a processorVerify the processorExpensiveNeed to iterateCustom ISACustom SDK(compiler,debugger,)Custom modelNeed large dedicated teamsIf you do i

4、t by handAutomationReady-to-modify IPAt Codasip we make it with:5 2023 Codasip.All rights reserved.Custom compute enabled by two componentsDesign automation toolFast architectural iteration loopProfiling&optimizationCo-simulationResults analysisUsing CodAL high-level languageGenerating custom RTL an

5、d SDKProduction-ready processorsWritten in CodALDesigned for customizationFully RISC-V compliantBest-in-class verificationAlso available as ready-to-use RTLDesign automation tools RISC-V Processor IPs6 2023 Codasip.All rights reserved.IP&tools combinationStart with a standard coreEmbedded and applic

6、ation coresHigh quality,production-readyFully RISC-V compliantDifferentiate with Codasip Studio Configure/ModifyUsing CodAL architecture description language Your application softwareCodasip RISC-Vcustomizable IPIn CodAL high-level languageCodasip StudioProfiling/analysisIA modelCA modelGeneratorHDK

7、SDKYour custom compute solutionLLVM C/C+compilerIA/CA executable modelsDebugger ProfilerRTLTestbenchEDA scriptsUVM environment7 2023 Codasip.All rights reserved.Hardware and software co-optimization accelerated through automationWrite/optimize codeCompileRun on executable modelProfile/Estimate perfo

8、rmanceOptimize HWIterate to find optimal hardwareVery long loop by handCodasip provides automationVery fast HW descriptionNo need to change codeAutomatic compiler generationAutomatic model generationSW ProfilingAccelerate process with Codasip automationOperation done with Codasip tools8 2023 Codasip

9、.All rights reserved.Get optimal results,fast.With an automated,iterative design processUpdate designFast high-level architecture loop(hours)Generate compilerProfile codeMicro-architecture loop(days)Profile codeGet instruction-accurate modelGet cycle-accurate modelRTL verification loop(days/weeks)Ge

10、nerate RTLGenerate TestbenchOptimized CPU designComplete SDK(compiler,debugger,models)Compile/run codeCompile/run codeCompile/run codeGet test code generatorAutomated by CodasipUser tasksFind optimizationsAdd micro-arch details in CodALDebugCheck constraintsVerify full design9 2023 Codasip.All rights reserved.Custom Compute is the best way forward nowSilicon process technology progress(Moores Law)has slowed downDifferentiation is vitalCustom compute brings10 x 100 xefficiency improvement from HW/SW co-optimizationThank you!2023 Codasip.All rights reserved.