1、Enabling compliance test for RISC-V BRSHaiboXuAndrei Warkentin Yin WangIntel ConfidentialDepartment or Event Name2RISC-V Summit China 20232Legal Notices and DisclaimersStatements in this document that refer to future plans or expectations are forward-looking statements.These statements are based on

2、current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements.For more information on the factors that could cause actual results to differ materially,see our most recent earnings release and SEC

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4、mes are often used by Intel to identify products,technologies,or services that are in development and usage may change over time.No license(express or implied,by estoppel or otherwise)to any intellectual property rights is granted by this document.Intel Corporation.Intel,the Intel logo,and other Int

5、el marks are trademarks of Intel Corporation or its subsidiaries.Other names and brands may be claimed as the property of others.This document contains information on products and/or processes in development.Intel ConfidentialDepartment or Event Name3RISC-V Summit China 20233Background With the grow

6、ing number of RISC-V implementations,there is a need for a standardized way to ensure interoperability across different RISC-V platforms RISC-V BRS specification defined some requirements(based on SBI/UEFI/ACPI/SMBIOS/DT etc.)for Boot and Runtime services that system software can rely on A complianc

7、e test suite can provide standardization and ensure that platform SW implementations adhere to the RISC-V BRS specification and maximize out of box software compatibility and interoperabilityIntel ConfidentialDepartment or Event Name4RISC-V Summit China 20234Current Status The RISC-V BRS Spec outlin

8、es requirements for Boot&RuntimeServices based on RVI and industry standard firmware interfaces https:/ Freeze Milestone Spec development stable Ratification Milestone Target Date Q4 23 The RISC-V BRS test suite checks for RISC-V platform compliance against BRSSpec based on UEFI-SCT and FWTS test su

9、ite https:/ Results on a Qemuvirtplatform was ready More test cases are under developmentPlatformHW/QEMUUEFIACPISMBIOSFWTSBRS test suiteOSFWUEFI SCTIntel ConfidentialDepartment or Event Name5RISC-V Summit China 20235UEFI SCT Results UEFI-SCT:Test framework for UEFI firmware compatibility.800+test ca

10、ses,5k+checkpoints from SCT test pool.Covers 75%UEFI case ofBRS spec.85%pass rate on RV64QemuVirtplatform.6846846 6333376761717UEFIUEFI-SCT results summarySCT results summaryPassFailWarnNot supportNo such caseIntel ConfidentialDepartment or Event Name6RISC-V Summit China 20236FWTS Results Designed t

11、o validate and test different aspects of firmware 700 test cases covering ACPI,SMBIOS,UEFI,Utilities 70%test cases were skipped on RISC-V platform for lacking corresponding ACPI tables and UEFI features1781785 517174 44944949 9FWTS results summaryFWTS results summaryPassFailAbortWarnSkipInfoIntel Co

12、nfidentialDepartment or Event Name7RISC-V Summit China 20237Key Gaps&Call to Action ACPI tables-(Qemu/UEFI/Kernel)PPTT/MCFG/SLIT/BERT/EINJ/ERST/HEST etc.Secure boot and variable(UEFI)Join the discussion and review for BRS specification https:/ https:/lists.riscv.org/g/tech-brs Collaborate on the rv-

13、brs-test-suite https:/ https:/ Linux/QemuACPI UEFI-SCT FWTSIntel ConfidentialDepartment or Event Name8RISC-V Summit China 20238RISE is focused on positive and transparent collaborations with upstream projects to deliver commercial-ready software for various use casesGoal:Goal:Accelerate open source

14、SW for RISC-V architectureHow:How:Align on highest priorities&avoid(accidental)duplication of work-https:/riseproject.devhttps:/ more interesting topics from Intel on RISC-V summit China 2023TopicTopicWhenWhenRISC-V Vector Support on ValgrindAugust 25 6pmBest practice to optimize SW with vectorization on RISC-VPosterRISC-V firmware solutionAugust 24 4:30pmEnhance UEFI on RISC-VAugust 24 4:20pmEnabling compliance test for RISC-V BRSAugust 24 3pm The ACRN/RISC-V project:embedded hypervisor design and status updateAugust 24 5pm