1、FORCE-RISCV Deploymenton XuanTie CPU VerificationProjectBinguang.Zhao/EthanForce-riscv Acting MaintainerWhats force-riscv？1XuanTie Deploy story2Force-riscv stage2 plan3CONTENTSWhats force-riscv？Python Frontend/C+backendPython fine grained templatesServer class cputop verificationDynamic Virtual Memo

2、ryMP scenario2020.6 Open source by FUTUREWEI.RV64G,F,D,C2022.2 v0.9/v1.0 released with RV32,paging fault,memory trait,vector 0.9 Dynamic InstructionSequencerSpike/SimulatorIntegratedRISCV RV64/32I,M,A,V2023.2 XuanTie starts stage 2 development:handcar/spike upgrade,vector 1.0,version control,mp 2023

3、.6 cmake build system ready Whats force-riscv？Provided by Futurewei:https:/ ISG:Output is ELF file can be directly loaded by env Instruction record feedback for fine-grained control Good coverage possible Hard to implementStatic ISG:Output is.s/.S file.Need toolchain Coarser granule controls bad cov

4、erage Easy to implementWhats force-riscv？Template:Command:Generated files:Gen.log:Fpix_sim.log:Whats force-riscv？Force-riscv infra:Memory ManagerVirtual Memory ManagerException:Triggers/handlersInstruction RecordsDependencyState Transition/Priviledge SwitchArch:Instructions/Registers/OperandsConfigB

5、nt ManagerReExe ManagerPhysical Page ManagerRegression systemThread Manager/Mp framework0 x50000000:ThreadSplitterSequence:split thread code0 x80000000+0 x100000 x thread_index:BootSequence:BootLoading sequence/backend0 x80011000+0 x1000000 x thread_index:EndOfTest:dead loopDynamic addresses:BranchN

6、otTaken:BranchNotTaken sequence/backendThreadSummary:ThreadSummary sequence/backend0 x80011000+0 x1000000 x thread_index:MainSequence:user sequenceDynamic address:exception handlersDynamic address:exception stackDynamic address:exception address tableupdateVMDynamic address:InitSetup sequence from b

7、ackendForce-riscv Instruction generation flow:Force-riscv instruction run-time execution flow:User genInstruction0 x50000000:ThreadSplitterSequence:split thread code0 x80000000+0 x100000 x thread_index:BootSequence:BootLoading sequence/backend0 x80011000+0 x1000000 x thread_index:MainSequence:user s

8、equence0 x80011000+0 x1000000 x thread_index:EndOfTest:dead loopNormal instructionBranch forward(branch not taken)Loop(branch backward,reexecute)Exception events(mret,sret,break,illegal)0 x80000000+0 x100000 x thread_index:InitSetupDeploy story infra+templstesArchitecture:Auto-generated ISA template

9、sVector/FP:knowledge based data patternPaging:dynamic page table,dynamic context switchMicro-arch:Branch:branch shadow,loopDependency:register,addressMemory:hw aware templatesMP:?cache?coherency?killerAssembly compiler,litmus portingMP zone based flow+golden memoryRandom sequence libraryML:AI based

10、coverage flow1234FORCEfrontendAPIsFORCEbackendHandcar/SpikeFORCE infra-AndroidFORCE templates-ApplicationsDeploy story issues of current version Build systemMakefile piler options are complex for cross-platform/ossupportModern IDE need to be supported Framework upgradeMulti configurations is hard to

11、 supportMP frameworkExtensions upgradeExisting extensions upgrades,vector1.0 New extensions support,RVA22?Handcar/Spike upgradeVersion control:patch scheme is hard to control,not friendlyLatest version merge is hardConfiguration choice scheme lack for implementation defined features00304D

12、eploy story XuanTie cpu projectInfrastructure UpgradeXxx,xxx cpu project deployArchitecture CompatibilityMain Apps FrameworkTemplates DevelopmentProject DeploymentCustom instruction groups,Inhouse sequence librariesVector infra,mp infra,tb handshake infra,Handcar/spike reconstructionConfig/builder u

13、pgradeCmake build system updateVersion control flow upgradePagingArchitecture:ISA,exception,virtual memory,mp,Micro-arch:lsu,branch,dependency,paging,mp,Extensions/Inhouse extensions upgradeImplementation defined features12345Thanks for PLCTs cooperation.Force-riscv stage2 plan with OpenHWList featu

14、re gapsProject proposalOpenHw reviewStep 01Project LaunchSpike upgradeCmake build systemVersion controlStep 02XuannTieOpensourceRVA22 new extensions?Existing extensions upgrade like vector1.0Say svpbmt,zicbo,zihintntl,hypervisor Step 03Extensions upgradeConfiguration/builder upgradesAssembly compile

15、rLitmus portingMp framework/gloden memoryTb handshakeVerification magicboxStep 04Framework upgrade T-HEAD FORCE-RISCV forked repos(early version will be released here):https:/ FORCE-RISCV repo:https:/ Former introduction materials:https:/ Stage2 proposal:https:/ FORCE-RISCV instance message system:url:https:/mattermost.openhwgroup.org/all-users/channels/town-squareCreate openhw/eclipse account guide:https:/www.openhwgroup.org/register/RISCV spec:Specifications:https:/riscv.org/technical/specifications/RVA22:https:/ MoreXuantie GitHubFORCE-RISCV TGDingTalk