1、Optimize Your Own RISC-V Architecture,Using Application-Specific Processor Design Tools:Synopsys ASIP Designer毛海雪,新思科技解决方案事业部，资深应用工程师August 25,2023 2023 Synopsys,Inc.2RISC-V Extensibility ISA customization and extensibility are drivers for the growing adoption of RISC-V This results in ASIPs with a

2、RISC-V baseline ISA Preserve RISC-V compatibility Execute SW code and libraries Reuse HW peripherals Challenges Which extensions are best for the target application domain?How to obtain a high-quality SW Development Kit(SDK),including an optimizing compiler?How to obtain a reliable RTL implementatio

3、n with excellent PPA?How to verify the design?Designed for general-purpose RISC-V 2023 Synopsys,Inc.3start trv32p5x;opn trv32p5x(bit32_ifmt|bit16_ifmt);opn bit32_ifmt(majOP|majOP_IMM|majLOAD|.|majCUSTOM3);opn majOP(alu_rrr_ar_instr|mpy_rrr_instr|div_instr);opn alu_rrr_ar_instr(op:majOP_fn10,rd:eX,rs

4、1:eX,rs2:eX)action stage ID:pidX1=r1=Xrs1;pidX2=r2=Xrs2;stage EX:aluA=pidX1;aluB=pidX2;switch(op)case add:aluR=add(aluA,aluB)alu;case sub:aluR=sub(aluA,aluB)alu;case slt:aluR=slt(aluA,aluB)alu;case sltu:aluR=sltu(aluA,aluB)alu;case xor:aluR=bxor(aluA,aluB)alu;.case sra:aluR=sra(aluA,aluB)alu;stage E

5、X:pexX1=texX1=aluR;stage ME:pmeX1=tmeX1=pexX1;stage WB:if(rd:x0)w1_dead=w1=pmeX1;else Xrd=w1=pmeX1;syntax:neg rd,rs2 op rs1|snez rd,rs2 op rs1|sltz rd,rs1 op rs2|sgtz rd,rs2 op rs1|op rd,rs1,PADOP2 rs2;image :op9.3:rs2:rs1:op2.0:rd,class(alu_rrr);.ASIP Designer Industry-leading tool to design your o

6、wn Application-Specific Instruction-set Processor(ASIP)Language-based description of ISA and microarchitecture:nML Single processor model ensures that SDK and RTL are in sync Architectural exploration with Compiler-in-the-Loop&Synthesis-in-the-Loop Licensed as a tool(not IP):product differentiation,

7、no royalties Full interoperability with other Synopsys EDA tools 2023 Synopsys,Inc.4Trv(RISC-V ISA)ModelsShipped with ASIP DesignerInteger models:Trvp ISA:RV64IM,RV32IM Integer and multiply instructions Micro architecture Protected pipeline,3 or 5 stages Hardware multiplier Iterative divider Optiona

8、l extensions:Trvpx Two-way static ILP Zero overhead hardware loops Load/stores with post-modify addressing32-bit datapath64-bit datapath3-stage pipelineTrv32p3Trv32p3xTrv64p3Trv64p3x5-stage pipelineTrv32p5Trv32p5xTrv64p5Trv64p5xFloating-point models:Trv32pf ISA:RV32IMZfinx Integer and multiply instr

9、uctions Single precision float instructions Micro architecture Protected pipeline,3 or 5 stages FPU models based on HardFloat Hauser Iterative divider and square-root units Optional extensions:Trv32pfx Two-way static ILP Zero overhead hardware loops Load/stores with post-modify addressing32-bit data

10、path3-stage pipelineTrv32p3fTrv32p3fx5-stage pipelineTrv32p5fTrv32p5fxTrv32p3xf +single-precision floating-point 1)2)+HW loop+post-mod+2-way ILP 1)pipeline depth:p3 or p5word length:32 or 641)optional2)Trv32 only 2023 Synopsys,Inc.5Trv Models With Simple Datapath eXtensions(SDX)SDX is a mechanism to

11、 add simple extension instructions to Trv(RISC-V)nML model of Trv32p3 with predefined stubs for extension instructions User codes the behavior of the stubs in PDG(bit-accurate C code)Compiler intrinsics that target the extension instructions are provided(and can be modified)Benefits No(deep)nML know

12、ledge required:extensions can be created by SW engineers Fast exploration of extensions with compiler-in-the-loop&synthesis-in-the-loop Extensions encoded in RISC-V custom-2 space Operand options 3-register(32 and 64-bit)Accumulate Additional single register inputs and outputsConceptX32i32DM8b/16b/3

13、2bX32i32ALUMPYDIVAGUTrv32p3sdxSDX0SDXNw32 sdx0(w32 a,w32 b)w32 r;r15:0=a15:0+b15:0;r31:16=a31:16+b31:16;return r;int sdx0(int,int);int add2(int,int);Behavioral model(PDG)Compiler intrinsics 2023 Synopsys,Inc.6Trv Models With Simple Datapath eXtensions(SDX)SDX Examples Provided With ASIP Designer Exa

14、mple:FFT SDX instructions accelerating Complex fixed-point multiplication&scalingsdx1 rd,rs1,rs2 ABS(x)function:sdx2 rd,rs1,rs2(x0)FFT Butterfly:sdx5 rd,rs1,rs1 Specialization:Fractional data types Complex numbers(16bit/16bit-32bit register)Speedup:280%Area increase:31%Example:SHA256 Computes a hash

15、 of message W using bitwise AND,OR,XOR operations,shift operations and additions Custom data path is ideal to implement the complex hash function in one instruction Additional state of the hash functions(8 state variables)require an SDX variant that supports 8 additional register reads and writessdx

16、7 rd,rs1,rs2,x24,x25,x32 Speedup:270%Area increase:16%Example:Keyword Spotting Based on small sized Neural Network(3.3M MACs)SDX architecture feature:packed SIMD 32-bit register contains vector of 4x 8-bit values Use of register pairs,enabling 64-bit accesssdx4a_dr dd,rs1,rs2,mode/vmacsdx0_dd rd,ds1

17、,ds2 /vqsat Speedup:1160%Area increase:16%X32i32X32i32ALUSHA stepXAXBXHXAXBXHX32i32X32i32ALUVMACXH32XL32XH32XL32i64i64VQSATX32i32DM8b/16b/32bX32i32ALUMPYDIVAGUFIX_MPYButterfly 2023 Synopsys,Inc.7Large-Scale Trv ExtensionsExample:“Tmoby”ASIP for Acceleration of MobileNet v3X32i32DM8b/16b/32bX32i32ALU

18、MPYDIVAGURV32IMxVAG RegsVM512b2D VG AGUVEC48u8MAT364u8VAG RegsVM LD/STVEC48u8MAT364u8WM512bVEC48u8MAT364u8WM AGUWAG RegsWAG RegsWM LD/STVEC48u8MAT364u8ACC364i32VEC48u8MAT364u8VMUL64:9bx9b=18bVADD64:add32ACC364i32VSHIFT64:lsl/asr+roundVector FUs VLIW extension of Trv32p3 90-bit instruction word 4-way

19、 ILP Scalar slot:Trv32p3 Vector arithmetic slot:SIMD64MAC 8x832 2 vector load/store slots:VM:featuresWM:weightsVector addressing 360 x cycle count decrease Acceleration through instruction-level parallelism,SIMD,and/or specialization By direct editing of any Trv model Typically results in VLIW archi

20、tecture with a RISC-V scalar issue slotApplication:MobileNet v3 Accelerated kernels:Conv_2D(pointwise)Depthwise_Conv_2DAddAverage_Pool_2DSoftmax 2023 Synopsys,Inc.8CoverityStatic check of ASIP Designer source code base ensures tool qualityVC FormalVerification of SystemVerilogproperties generated by

21、 ASIP DesignerDesignWare LibrariesLibrary components can be incorporated in ASIP processor modelASIP Designer Tightly Integration with Synopsys Flows Automatic Generation of Interfaces Reduces Overall Time-to-ResultsVirtualizer&Platform ArchitectSoC architecture design and pre-silicon SW development

22、,using SystemC wrapped ISS of ASIPZebuPlayback in ASIP Designer-generated ISS,using Zebu-generated tracing infoDesign Compiler&Fusion CompilerImplementation of ASIP Designer-generated RTL,with best PPA RTL ArchitectFast and accurate PPA estimation of ASIP Designer-generated RTLZebu&HAPSHigh-speed verification and FPGA prototyping with SW debug support,of ASIP Designer-generated RTLVerdi HW/SW DebugDebugger connected to RTL simulator with playback supportSpyglassLinting of ASIP Designer-generated RTLHAPS 70/80JTAGASIPPDCZebuJTAG XTORASIPPDCJTAG XTORServerThank You