1、Zonal Architecture and New Opportunities to Optimize the Cost and Power of Interzonal Links Alireza Razavi,Ragnar Jonsson,David Shen|MarvellIEEE SA Ethernet&IP Automotive Technology Day19-20 September 2023,So Paulo,Brazil 2023 Marvell.All rights reserved.2Point to point,rigid,expensiveDomainsEtherne

2、tNetworked,secure,scalable,intelligentZonesDomain-based vs.zonal architecture 2023 Marvell.All rights reserved.3DomainsPoint-to-point links are longZonal links are shorterZonesEthernetInterzonal links are short 2023 Marvell.All rights reserved.4Point-to-point vs.interzonal link attributesPoint-to-po

3、int15m:1000/2.5G/5G/10GBASE-T111m:25GBASE-T1 Up to four inline connectorsInterzonalMuch shorter(less than 5m)Fewer inline connectorsSensorProcessor15m cableSensorBridge 2023 Marvell.All rights reserved.5Short-reach interzonal links ideal for camera-bridgeCamera Bridge is subject of recent 802.3 stud

4、y groupBridge 2023 Marvell.All rights reserved.6Typical full-duplex linkCoderEqualizer/coderAnalog to digital convertorDigital to analog convertorEcho cancelerTransmitbitsReceivedbitsHybridLink partner 2023 Marvell.All rights reserved.7What we want to optimize Power consumptionSilicon area(cost)Lowe

5、r power and area means lower complexity 2023 Marvell.All rights reserved.815mLower insertion loss=simpler equalizationSource:Marvell5m 2023 Marvell.All rights reserved.9Lower insertion loss=less echo cancelation neededSource:Marvell 2023 Marvell.All rights reserved.10Shorter echo duration=simpler ec

6、ho cancelers15m cableSensorProcessorBridgeSensor 2023 Marvell.All rights reserved.11How can we take advantage of the shorter link?Enjoy higher design margin1Use less expensive cable2ORReduce PHY power and/or area3OR 2023 Marvell.All rights reserved.12Use less expensive cableCoderEqualizer/decoderADC

7、DACEcho cancelerTransmitbitsReceivedbitsHybridLink partnerLower quality cable 2023 Marvell.All rights reserved.13Power savings possible under current standards Chip area savings not possible with current standardsStill need to support longer cables CoderEqualizerADCDACTransmitbitsReceivedbitsHybridL

8、ink partnerShorter cableSimpler analog frontendShorter echo cancelerSimpler equalizerEcho canceler 2023 Marvell.All rights reserved.14What ifwe optimized design for interzonal links?Optimize equalization and echo cancellation circuitsUse lower baud rate,higher-order modulation Power and area savings

9、 Power savings:f(baud rate)Reduced need for HW parallelism=area savings 2023 Marvell.All rights reserved.15Echo cancelerEcho cancelerEcho cancelerEqualizer&decoderEqualizer&decoderEqualizer&decoderEcho cancelerEcho cancelerEcho cancelerADCDACADCDACADCDACLower baud rate reduces HW requirements CoderE

10、qualizer&decoderEcho cancelerTransmitbitsReceivedbitsHybridLink partnerADCDAC 2023 Marvell.All rights reserved.16UpstreamDownstreamRequirementsData Rate Gbps:1010Target RS-FEC output BER:1.00E-121.00E-12Cable Length m:5.0005.000Wire u-reflections limit:jonsson*12_08_20 jonsson*12_08_20Number of Conn

11、ectors:44ModulationPAM Levels:1616FEC Block Size(n):360360FEC Data Size(k):326326RS-FEC Correction Efficiency:100%100%Bits per FEC Symbol:1010TDD Time Duty-Cycle:100%100%Framing Overhead:1.875%1.875%Transmit SignalPSD-mask:PSD_ZOHPSD_ZOHTransmit Power dBm:00Design TradeoffImpulse Error Rate:1.00E-04

12、1.00E-04AFE-noise dBm/Hz:-140-140Cable Reflection Echo Cancelation dB:66Connector Echo Cancelation dB:5050Implementation Loss dB:55Simulation ParametersCable Model:PCB model:PCB trace length m:Connector Echo Model:Temperature C:Max Simulation Frequency:Calculated ValuesUpstreamDownstreamTheoretical

13、Slicer SNR dB:36.3936.39Estimated Slicer SNR dB:31.3931.39Required Slicer SNR dB:29.0929.09SNR Margin dB:2.302.30Wire u-reflections dB:-35.00-35.00Nyquist Frequency GHz:1.411.41Channel Insertion Loss Nyquist dB:6.146.14Cable Insertion Loss Nyquist dB:5.605.60Hard5.00E+09mueller_3cy_01_12_01_20_stp20

14、pcb_kadry_3cy_02_08200.0762UpstreamDownstreamRequirementsData Rate Gbps:1010Target RS-FEC output BER:1.00E-121.00E-12Cable Length m:15.00015.000Wire u-reflections limit:jonsson*12_08_20 jonsson*12_08_20Number of Connectors:44ModulationPAM Levels:44FEC Block Size(n):360360FEC Data Size(k):326326RS-FE

15、C Correction Efficiency:100%100%Bits per FEC Symbol:1010TDD Time Duty-Cycle:100%100%Framing Overhead:1.875%1.875%Transmit SignalPSD-mask:PSD_ZOHPSD_ZOHTransmit Power dBm:00Design TradeoffImpulse Error Rate:1.00E-041.00E-04AFE-noise dBm/Hz:-140-140Cable Reflection Echo Cancelation dB:66Connector Echo

16、 Cancelation dB:5050Implementation Loss dB:55Simulation ParametersCable Model:PCB model:PCB trace length m:Connector Echo Model:Temperature C:Max Simulation Frequency:Calculated ValuesUpstreamDownstreamTheoretical Slicer SNR dB:26.6926.69Estimated Slicer SNR dB:21.6921.69Required Slicer SNR dB:17.20

17、17.20SNR Margin dB:4.494.49Wire u-reflections dB:-42.79-42.79Nyquist Frequency GHz:2.812.81Channel Insertion Loss Nyquist dB:28.8028.80Cable Insertion Loss Nyquist dB:27.7927.79Hard5.00E+09mueller_3cy_01_12_01_20_stp20pcb_kadry_3cy_02_08200.0762Use 802.3cy tool to compare PAM4 and PAM16 2023 Marvell

18、.All rights reserved.17UpstreamDownstreamRequirementsData Rate Gbps:1010Target RS-FEC output BER:1.00E-121.00E-12Cable Length m:15.00015.000Wire u-reflections limit:jonsson*12_08_20 jonsson*12_08_20Number of Connectors:44ModulationPAM Levels:44FEC Block Size(n):360360FEC Data Size(k):326326RS-FEC Co

19、rrection Efficiency:100%100%Bits per FEC Symbol:1010TDD Time Duty-Cycle:100%100%Framing Overhead:1.875%1.875%Transmit SignalPSD-mask:PSD_ZOHPSD_ZOHTransmit Power dBm:00Design TradeoffImpulse Error Rate:1.00E-041.00E-04AFE-noise dBm/Hz:-140-140Cable Reflection Echo Cancelation dB:66Connector Echo Can

20、celation dB:5050Implementation Loss dB:55Simulation ParametersCable Model:PCB model:PCB trace length m:Connector Echo Model:Temperature C:Max Simulation Frequency:Calculated ValuesUpstreamDownstreamTheoretical Slicer SNR dB:26.6926.69Estimated Slicer SNR dB:21.6921.69Required Slicer SNR dB:17.2017.2

21、0SNR Margin dB:4.494.49Wire u-reflections dB:-42.79-42.79Nyquist Frequency GHz:2.812.81Channel Insertion Loss Nyquist dB:28.8028.80Cable Insertion Loss Nyquist dB:27.7927.79Hard5.00E+09mueller_3cy_01_12_01_20_stp20pcb_kadry_3cy_02_08200.0762UpstreamDownstreamRequirementsData Rate Gbps:1010Target RS-

22、FEC output BER:1.00E-121.00E-12Cable Length m:5.0005.000Wire u-reflections limit:jonsson*12_08_20 jonsson*12_08_20Number of Connectors:44ModulationPAM Levels:1616FEC Block Size(n):360360FEC Data Size(k):326326RS-FEC Correction Efficiency:100%100%Bits per FEC Symbol:1010TDD Time Duty-Cycle:100%100%Fr

23、aming Overhead:1.875%1.875%Transmit SignalPSD-mask:PSD_ZOHPSD_ZOHTransmit Power dBm:00Design TradeoffImpulse Error Rate:1.00E-041.00E-04AFE-noise dBm/Hz:-140-140Cable Reflection Echo Cancelation dB:66Connector Echo Cancelation dB:5050Implementation Loss dB:55Simulation ParametersCable Model:PCB mode

24、l:PCB trace length m:Connector Echo Model:Temperature C:Max Simulation Frequency:Calculated ValuesUpstreamDownstreamTheoretical Slicer SNR dB:36.3936.39Estimated Slicer SNR dB:31.3931.39Required Slicer SNR dB:29.0929.09SNR Margin dB:2.302.30Wire u-reflections dB:-35.00-35.00Nyquist Frequency GHz:1.4

25、11.41Channel Insertion Loss Nyquist dB:6.146.14Cable Insertion Loss Nyquist dB:5.605.60Hard5.00E+09mueller_3cy_01_12_01_20_stp20pcb_kadry_3cy_02_08200.0762Use 802.3cy tool to compare PAM4 and PAM16UpstreamDownstreamRequirementsData Rate Gbps:1010Target RS-FEC output BER:1.00E-121.00E-12Cable Length

26、m:5.0005.000Wire u-reflections limit:jonsson*12_08_20 jonsson*12_08_20Number of Connectors:44ModulationPAM Levels:1616FEC Block Size(n):360360FEC Data Size(k):326326RS-FEC Correction Efficiency:100%100%Bits per FEC Symbol:1010TDD Time Duty-Cycle:100%100%Framing Overhead:1.875%1.875%Transmit SignalPS

27、D-mask:PSD_ZOHPSD_ZOHTransmit Power dBm:00Design TradeoffImpulse Error Rate:1.00E-041.00E-04AFE-noise dBm/Hz:-140-140Cable Reflection Echo Cancelation dB:66Connector Echo Cancelation dB:5050Implementation Loss dB:55Simulation ParametersCable Model:PCB model:PCB trace length m:Connector Echo Model:Te

28、mperature C:Max Simulation Frequency:Calculated ValuesUpstreamDownstreamTheoretical Slicer SNR dB:36.3936.39Estimated Slicer SNR dB:31.3931.39Required Slicer SNR dB:29.0929.09SNR Margin dB:2.302.30Wire u-reflections dB:-35.00-35.00Nyquist Frequency GHz:1.411.41Channel Insertion Loss Nyquist dB:6.146

29、.14Cable Insertion Loss Nyquist dB:5.605.60Hard5.00E+09mueller_3cy_01_12_01_20_stp20pcb_kadry_3cy_02_08200.0762UpstreamDownstreamRequirementsData Rate Gbps:1010Target RS-FEC output BER:1.00E-121.00E-12Cable Length m:5.0005.000Wire u-reflections limit:jonsson*12_08_20 jonsson*12_08_20Number of Connec

30、tors:44ModulationPAM Levels:1616FEC Block Size(n):360360FEC Data Size(k):326326RS-FEC Correction Efficiency:100%100%Bits per FEC Symbol:1010TDD Time Duty-Cycle:100%100%Framing Overhead:1.875%1.875%Transmit SignalPSD-mask:PSD_ZOHPSD_ZOHTransmit Power dBm:00Design TradeoffImpulse Error Rate:1.00E-041.

31、00E-04AFE-noise dBm/Hz:-140-140Cable Reflection Echo Cancelation dB:66Connector Echo Cancelation dB:5050Implementation Loss dB:55Simulation ParametersCable Model:PCB model:PCB trace length m:Connector Echo Model:Temperature C:Max Simulation Frequency:Calculated ValuesUpstreamDownstreamTheoretical Sl

32、icer SNR dB:36.3936.39Estimated Slicer SNR dB:31.3931.39Required Slicer SNR dB:29.0929.09SNR Margin dB:2.302.30Wire u-reflections dB:-35.00-35.00Nyquist Frequency GHz:1.411.41Channel Insertion Loss Nyquist dB:6.146.14Cable Insertion Loss Nyquist dB:5.605.60Hard5.00E+09mueller_3cy_01_12_01_20_stp20pc

33、b_kadry_3cy_02_08200.0762 2023 Marvell.All rights reserved.18Areas for further studyElectromagnetic noiseError correction codes/latencyJitter sensitivity 2023 Marvell.All rights reserved.19Key takeaways1234Existing standards designed for point-point and backbone networkZonal architecture:most links are between sensors and local switchesCurrent Ethernet PHYs are overdesigned for interzonal linksStandards evolution would enable PHY optimization for interzonal linksThank You 2023 Marvell.All rights reserved.22Special thanks to Mark Davis for his valuable inputs