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1、Scaling into the Next DecadeRebecca K.Schaevitz,PhDBroadcom Optical Systems Division2Long-haul80 kmDirect Attach Copper Cable(2m)Active Optical Cable(30m)Parallel Single-mode Fiber(2 km)Duplex&ParallelSingle-mode Fiber(80 km)OpticalElectrical3DFE deci si on f eedback equal i zerFFE f eed f or war d
2、equal i zerDSP di gi t al si gnal pr ocessorMLSE maxi mum l i kel i hood sequence est i mat i on equal i zerI L i nser t i on l ossDAC di r ect at t ach copper cabl eOBO on-boar d opt i csBOW/D2D bunch of wi r es/di e t o di eXSR ext r emel y shor t r eachVSR ver y shor t r eachLR l ong r eachCPO co
3、-packaged opt i csFPP f acepl at e pl uggabl e4Engineering and manufacturing limits to scaleCONVENTIONAL MODULE DESIGNModule Integration=First step to improved scaleINTEGRATED MODULE DESIGN BASED W/SCIPHighly Integrated Optical Engines(3.2T to 6.4T)CO-PACKAGED OPTICS30%fewer Piece Parts!SiPh Chiplet
4、s in Package(SCIP)Fiber JumperPhy IChttps:/ TYPERELATIVE COSTDACAOCPSMRELATIVE COSTS OF COPPER VS OPTICS(TODAY)CapEx GulfUn-retimed copper(DAC)is simpleDAC cost significantly lower than alternativesCopper challenged as data rates increaseAdvanced photonic integration narrows gapCo-packaging drives O
5、pEx efficienciesLower power consumptionExpected higher reliability Reduced operational burdenAssessing TCO for Optics is Complex6Who Does What?Co-packagingOpticsFiberASICPCBOpticsFiberASICPCBElectrical7Co-PackagingIntegration of multiple dies on a common package substrateHigh volume use cases today
6、like HBM*Source:Image,AMD,https:/ Source:Yole Developpement,http:/www.yole.fr/3D_25D_Stacking_Technologies_IntelEMIB.aspx#.YJyx7pNKh25 Co-Packaged OpticsIntegration of optical engines on a common package substrateObjective:alleviate the“interconnect density bottleneck”PCBAPackage SubstrateASIC,CPU,G
7、PUOptical EngineElectrical LinkOptical LinkGPU/CPU/SoC DiePackage SubstrateInterposerLogic DiePHYPHYHBM DRAM DieHBM DRAM DieHBM DRAM DieHBM DRAM DieTSVMicrobumpHBM:High Bandwidth MemoryTSV:Through Silicon ViasHBM:High Bandwidth MemoryTSV:Through Silicon Via8Reference:https:/ Stacked dieOptical engin
8、eASICSubstrateHBM2013:Bringing the memory on packageCPO2022:Bringing the TB optical IO on package9Co-packaging meets the density challengeEscape Density vs.Power Efficiency051015202500.050.10.150.20.250.30.350.40.45FPPOBONPOCPOWDM CPO(Gen 1)WDM CPO(Gen 2)Power,pJ/bitEscape Density,1/mmEscape Density(3.2T)Power EfficiencySiPh Chiplets In-Package(SCIP)FPP:Front Panel PluggableOBO:On-board opticsNPO:Near package opticsWDM:Wavelength division multiplexingOver the next 5 years,this 400G NIC needs to drive to 800G,1.6T and 3.2T in the same form factor.