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1、ISSCC 2024SESSION 3Analog Techniques 3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference1 of 60A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125CPangi Park1,Junghyup Lee2and
2、 SeongHwan Cho11 KAIST,Daejeon,Korea2 DGIST,Daegu,Korea3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference2 of 60Outline Introduction Key idea Sub-ranging compensation Proposed architectureProposed TC-contro
3、llable IR(,T)Circuit implementation Measurement results Conclusion3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference3 of 60Temperature-stable IREFis essential for reliable system operation.MotivationTypical
4、 analog ICs in systemsIREF ADCNTCHallBiasingcircuitsBiasingsensorsElectronic Device temperature ratingsIndustrial4085 CAutomotive40125 CCommercial070 C*Icons from Flaticon*https:/ PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State C
5、ircuits Conference4 of 60TemperatureCurrentTrangeIPTATICTATGeneration of Temperature-stable IREFIREF=IPTAT+ICTATIIPTATand ICTAThave oppositetemp.dependenciesBy adjusting their slopes,we can minimize I over Trange 1st-order TC compensated IREFis obtained.*TC:temperature coefficients3.1:A PVT-Insensit
6、ive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference5 of 602nd-order TC compensation is necessary for wide-range operation.TemperatureCurrentTrangeIPTATICTATDesign Challenges in Wide Temp.RangeI Problem:2nd-order TCNon-linear
7、increase in Iwith expansion of temp.range(Curvature)IREF=IPTAT+ICTAT3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference6 of 60TemperatureIREFT1T2T3TemperatureIREFT1T2T3ProcessVariationThree-point TrimmingThr
8、ee-point trimming of IREFProblem:Process variation in TCsNeed chip-by-chip trimming Increase of production cost Process-insensitive 2nd-order TC comp.technique is necessary.3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Ci
9、rcuits Conference7 of 60Design Goals for Current Reference Curvature correction for high-temperature stabilityacross a wide temp.range Process-insensitive TC compensation Small overhead (e.g.w/o additional reference)3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to
10、125C 2024 IEEE International Solid-State Circuits Conference8 of 60Prior WorksH.Banba,JSSC99=+Current-sum based compensationTIPTATICTATTC of IREFR11:NIREF VBEVBER2R2IPTATICTAT Curvature remains Large process variation in TC No additional referenceRIREF VCOMPGen.BGRVCOMPJ.Lee,JSSC121st-order TCMatchi
11、ng(TCVTCR)Division-based compensation Curvature remains(24.9 ppm/C,0100C)Small process-variation in TC Need additional BGR=(+)(+)TTC of IREFRVCOMP3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference9 of 60VCO
12、MPCIREFRSTTININTPrior WorksS.Danesh,JSSC19=Curvature-corrected(3.2 ppm/C,-4085C)Small process variation in TC Crystal and BGR are requiredPMOS-only zero-TC biasingQ.Dong,ESSCIRC17=VZTCIREFVSGILow-TVZTCIREFHigh-T Large curvature remains(262 ppm/C,-40120C)Small process variation in TC No additional re
13、ference Curvature-CorrectedBGRVCOMP CLKGen.fXOTININTRSTCurvature-corrected division-based comp.TININTRSTfXO3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference10 of 60Summary and Design GoalsTargetsCurrentSum
14、 basedDivision-basedCurvature-correctedDivision-basedPMOS-onlyZTC-biasingDesignGoalsTemp.StabilityProcessVariationOverhead Our goal is to meet all the targets.3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Confere
15、nce11 of 60Outline Introduction Key idea Sub-ranging compensation Proposed architectureProposed TC-controllable IR(,T)Circuit implementation Measurement results Conclusion3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circ
16、uits Conference12 of 60TIT1T2TIIR(T)T1TT2Full RangeIR(T)Conventional Full-range Compensation Curvature remains over the full temperature range.3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference13 of 60IR(,T
17、)1 2 TC-programmableCurrent source SELIR10TIT1T2Range 1 Range 2Sub-rangesIR(1)IR(2)TIT1T2Range 1 Range 2Sub-rangesProposed Concept Sub-ranging Compensation Divide the full range into sub-ranges and pensation for each sub-range3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C fr
18、om-20C to 125C 2024 IEEE International Solid-State Circuits Conference14 of 60TIT1T2Range 1 Range 2Sub-rangesIR(1,T)1 2 TC-programmableCurrent source SEL=0IR(1,T)10IR(,T)Proposed Concept Sub-ranging Compensation 1gives good TC in Range 1 but poor TC in Range 2.Good TCPoor TC3.1:A PVT-Insensitive Sub
19、-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference15 of 60TIT1T2Range 1 Range 2Sub-rangesIR(2,T)IR(1,T)IR(,T)1 2 TC-programmableCurrent source SEL=110IR(2,T)Proposed Concept Sub-ranging Compensation 2gives good TC in Range 2 but po
20、or TC in Range 1.Poor TCGood TC3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference16 of 60IR(,T)1 2 TC-programmableCurrent source IR(T)10TTXSub-rangeDetectorTIT1T2 1 2Sub-rangesIR(2,T)IR(1,T)TXTransition at
21、TX By making transition at the temperature TX,we can obtain good TC across the full-range.Proposed Concept Sub-ranging CompensationIR(T)3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference17 of 60 Curvature c
22、an be reduced by up to 1/4.TIT1T2TXw/sub-rangingw/o sub-rangingReduced Curvature After Compensation For 2nd-order TC,midpoint transition is optimal.ICURVICURVICURV4=3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits C
23、onference18 of 60Effect of Process Variation Discontinuity Abrupt current change occurs at the midpoint.TIT1T2TXIR(2,T)IR(1,T)DiscontinuityIR(T)3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference19 of 60TIT2
24、TXTXT1IR(2,T)IR(1,T)Effect of Process Variation TC Degradation No discontinuity,but IRexhibits a large TC.Large TCIR(T)3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference20 of 60Design Goals for Sub-ranging
25、Compensation Process-insensitive seamless midpoint transition.TIT1T2IR(1)IR(2)TX2.Seamless transition3.Midpoint TX1.Process-insensitivity3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference21 of 60Outline Int
26、roduction Key idea Sub-ranging compensation Proposed architectureProposed TC-controllable IR(,T)Circuit implementation Measurement results Conclusion3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference22 of 6
27、0TIR(,T)=0=5=10=15=20=25Basic Structure for IR(,T)Generation,=()+()()=,=()()=,=()+()()There is no intersection within the practical temp.range.Sub-ranging is not applicable.VPTAT(T)VCTAT(T)R(T)12IR(,T)A larger results in a more PTAT characteristic3.1:A PVT-Insensitive Sub-Ranging Current Reference A
28、chieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference23 of 60 Intersection occurs at TXwithin the practical temp.range.Sub-ranging is applicable at TX.Proposed Structure for IR(,T)Generation,=()+()+=0=5=10=15=20=25TIR(,T)TX=,=,=+Intersection exists!12VPTAT(T)VCT
29、AT(T)R1(T)R2(T)IR(,T)Resistance in denominator also increases with 3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference24 of 60Proof:IR(,T)intersects at one point regardless of,=()+()()+()=+If()()=()()holds a
30、t a temperature TX independent of at TX(,)=()()=()()At T=TX All(,)graphs intersect at TXregardless of.=0=5=10=15=20=25TIR(,T)TX3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference25 of 60Determination of TXLo
31、cation We can obtain process-insensitive midpoint TX.()()=()()TXis whereNearly constant over temp.if R1,R2are the same type.TXTT1T2VCTAT(T)VPTAT(T)R2(T)R1(T)Find the optimal R2/R1that gives midpoint TXRatio of parameters Process-insensitiveTXis process-insensitive!3.1:A PVT-Insensitive Sub-Ranging C
32、urrent Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference26 of 60TXIR(,T)T1T2T Since TXis independent of,we have the freedom to chooseany that minimizes TC for each sub-range.Selection of 1and 2for Each Sub-rangeIR(2,T)for TXTT2IR(1,T)for T1TTXIR(,
33、TX)3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference27 of 60TXIR(,T)T1T2T With the proposed IR(,T),we can achieve process-insensitive,seamless,and midpoint transition for sub-ranging.Sub-ranging IRbased on
34、 Proposed IR(,T)IR(,TX)Process-tolerance Seamless Midpoint transition3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference28 of 60Outline Introduction Key idea Sub-ranging compensation Proposed architecturePro
35、posed TC-controllable IR(,T)Circuit implementation Measurement results Conclusion3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference29 of 60R11:NIRVBEConventional PTAT and CTAT Current SourcesPTAT current so
36、urce Same structure except for the load connected to OP+.TITICTAT current source=R2IRVBE3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference30 of 60TIProposed TC-interpolating Current Reference A mid-TC betwe
37、en PTAT and CTAT sources is obtained.IRvs temperatureR11:NR2IREFk1-k(0k1)1:1:1TC interpolationV1V23.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference31 of 60R11:NR2IREFk1-kTIOperation Principle of TC-interpo
38、lation When k=1,IRhas a TC of conventional PTAT source.k=1k=1PTAT1:1:1IRvs temperatureV1V23.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference32 of 60R11:NR2IREFk1-kTIOperation Principle of TC-interpolation W
39、hen k=0,IRhas a TC of conventional CTAT source.k=0k=1k=0CTAT1:1:1IRvs temperatureV1V23.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference33 of 60TIOperation Principle of TC-interpolation When 0k1,IRhas an int
40、erpolated TC.k=0k=1()()R11:NR2IREFk1-k0kR1,R2)Simple Realization of TC Interpolation Interpolation is implemented by internal division of R3.R11:NR2IREF(1-k)R3kR31:1:1TIk=0k=1()()IRvs temperatureV1V2V3*Negligible currentacross R33.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C
41、 from-20C to 125C 2024 IEEE International Solid-State Circuits Conference35 of 60Derivation of IRR11:NR2IREF(1-k)R3kR3(R3R1,R2)VBE1+-VBE21:1:1=+=+=(Negative feedback)(=,=)=+V1V2V3 Note:IRis supply insensitive3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 202
42、4 IEEE International Solid-State Circuits Conference36 of 60 Proposed structure can be realized by the proposed circuit.Comparison to the Proposed EquationProposed structure for sub-rangingVPTATVCTATR1R212(=,=)VPTATVBEVCTATVBEk1k=+Derived IRof proposed circuit=+3.1:A PVT-Insensitive Sub-Ranging Curr
43、ent Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference37 of 601:NIR(k,T)R3Process-insensitive Sub-ranging IR(,)=+-VBE1+-VBE2 TXis process-insensitive since it is determined by the ratios.R1R2k1k2Midpoint TXcan be set by adjusting R1:R2TXVBE(T)VBE(T
44、)TV(T)T1T2R1:R2TXis determined where VBE:VBE=R1:R2holds 3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference38 of 60TXTIR(k,T)T1T21:NIR(k,T)R3Process-insensitive Sub-ranging IR(,)=+-VBE1+-VBE2 k is also proce
45、ss-insensitive since it is internal division ratio of R3.R1R2k1k2IR(k1,T)and IR(k2,T)are crossed at TXIR(k1,T)IR(k2,T)3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference39 of 60TXTIR(k,T)T1T2IR(k,T)k1 k2 TC-
46、programmableCurrent source IR(k,T)10TTXSub-rangeDetectorSub-range Detector Need a temp comparator whose threshold is TX.?Need transition at TXRealized by proposed circuitIR(k1,T)IR(k2,T)3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International S
47、olid-State Circuits Conference40 of 60V1V2R1R2VBE1VBE2IR1:1:1:1(R3R1,R2)V31:N(1-k)R3k R3SELKInherently Process-insensitive Sub-range Detector Sub-range detection is achieved by just comparing V1and V2.TTXIk2IRk1TXVTT1T2SELK3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-
48、20C to 125C 2024 IEEE International Solid-State Circuits Conference41 of 60Equality of V1and V2at T=TX At T=TX,IRis independent of k.V1=V2=V3=VBE T=TXTIRTXIR(k,TX)=IR(k,TX)IRvs temperatureVBE1=V3(k)V1V2R1R2VBE1VBE2IR1:1:1:1(R3R1,R2)1:N(1-k)R3k R3V3(k)3.1:A PVT-Insensitive Sub-Ranging Current Referen
49、ce Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference42 of 60V1V2R1R2VBE1VBE2IREF1:1:1:1(R3R1,R2)V31:N(1-k)R3k R3SELKTC difference of V1and V2 Inherently precise sub-range detection is achieved.=CTATTTXVSELKV1V2TCV1R1,R2)V31:NProposed Sub-ranging Current Ref
50、erence Process-insensitive seamless midpoint transition is achieved!TTXITTXk=k2k2IREFk1TXVTT1T2V1V2SELK3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference44 of 60Transistor-level SchematicChopping&DEM:To red
51、uce offset-induced TC variation and 1/f noise.RBat the base of Q1:To mitigate effect of temperature-dependent of BJTs.R1R2Q2Q1RBCC1RSIREFV1V2DEMk-SelectorCHCHCHCHCHV3R3=6.5M VB(6.2k)(67.8k)(1.24k)(43.8k)Error amplifierCurrent Generation&MirrorBias Gen.1:1:1:1CC2IB1:202IB1:8Types of resistorsR1,R2,RB
52、P+poly w/o silicideR3HRI poly resistorB.Wang JSSC 223.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference45 of 60Transistor-level Schematic k-selector Hysteresis comparator:To avoid noise-induced switching.Fol
53、ded RDAC:A portion of R3is designed as a DAC to change k.Comparator6b Folded RDACk-SelectorC7C6C0R7R6R0V1V2V30.89R30.08R3V2V1VBSELKR7:0V2V1C7:0k1k2SELK10Row-ColDecoderFolded RDACV33.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-S
54、tate Circuits Conference46 of 60Outline Introduction Key idea Sub-ranging compensation Proposed architectureProposed TC-controllable IR(,T)Circuit implementation Measurement results Conclusion3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE Internati
55、onal Solid-State Circuits Conference47 of 60Chip Photo290 m273 mCOMPErrorAMPRDACk-SELCcR3BJTCKGENR1,R2,RBCurrent MirrorTEST Process:180nm CMOS Area:0.08mm2Full-chip Micrograph1160m910m3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Sol
56、id-State Circuits Conference48 of 60Measurement SetupInside of the chamber-Func.Gen(Keysight 33600A)-Source Meter(Keithley 2400)-Power Supply(Keisight B2962A)-NI Labview DAQ(USB-6211)SPITemp.Chamber(-20 to 125C)PowerCLK Chamber test is conducted to evaluate temperature dependency.3.1:A PVT-Insensiti
57、ve Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference49 of 60-20020406080100125Temperature(C)10.210.2210.2410.2610.2810.310.3210.3410.36IREF(A)IREF with Different kBest TC:28.6ppm/C 7.81ppm/CkC=20kC=24kC=29kC=35kC=40kC=44kC=47Be
58、st TC w.o.sub-ranging:kC=35Measured IREFvs Temp.with different k 1storder TC can be controlled by k-code(kC)TX 50C and best TC=28.6ppm/C where k=0.905R3SELKV1V2R1R2VBE1VBE2IREF1:1:1:1(R3R1,R2)V31:NDifferent k3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 202
59、4 IEEE International Solid-State Circuits Conference50 of 60 Best TC=28.6 7.81ppm/C where k1=0.901,k2=0.0100125Temperature(C)10.210.2210.2410.2610.2810.310.3210.3410.36IREF(A)IREF with Different kBest TC:28.6ppm/C 7.81ppm/CBest TC w.o.sub-ranging:kC=35Best TC with sub-ranging:kC1=24,kC
60、2=44kC=20kC=24kC=29kC=35kC=40kC=44kC=47R3SELKV1V2k2k1R1R2VBE1VBE2IREF1:1:1:1(R3R1,R2)V31:NMeasured IREFvs Temp.with Sub-ranging3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference51 of 60R3SELKV1V2k2k1R1R2VBE
61、1VBE2IREF1:1:1:1(R3R1,R2)V31:N-20020406080100125Temperature(C)0.40.450.50.550.60.650.70.750.80.850.9V1,V2(V)V1,V2 and SELKV1V2IREFSELK=1SELK=0Measured Operation of Sub-range Detector As expected,V1and V2are crossed at T=TX3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-2
62、0C to 125C 2024 IEEE International Solid-State Circuits Conference52 of 60Measured Line and Load Sensitivity of IREF Line Sensitivity:365ppm/V,Load Sensitivity:181ppm/V00.30.60.91.21.51.8VLOAD(V)Load SensitivityVLOAD Range:0V-0.7VTTFFSSFSSF024681000.30.60.9VLOAD(V)10.2510.310.3510.4IREF(A)Load Sensi
63、tivity(ppm/V)TT FF SS FS SF AVG 175 250 141 146 191 181 Line Sensitivity(ppm/V)TT FF SS FS SF AVG 388 394 339 321 382 365 3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference53 of 60Batch Calibration for k1an
64、d k2Selection202k1_code424344454647484950k2_codeg 2Temperature Coefficient(ppm/C)Average TC of the batch for different k1 and k2 45 Chips are measured From 5 corner wafers(TT:25,FF/SS/SF/FS:5 each)VDD=1.8V,VLOAD=0.3V Lowest TC at kC1=24(k1=0.901)and kC2=45(k2=0.9084)Best TCHigh
65、 temp.(50125 C)Low temp.(-2050 C)3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference54 of 6010.1510.210.2510.310.3510.410.4510.510.55-20020406080100125Temperature(C)IREF(A)Measured IREFTTFFSSFSSF0.99850.9990
66、.999511.00051.0011.00151.0021.00251.0100125Temperature(C)Normalized IREFTTFFSSFSSF3 Normalized IREF at 50CMeasured IREFwith fixed k1and k2 3-temp.variation of 0.2%is achievedTX(No trim)0.2%3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEE
67、E International Solid-State Circuits Conference55 of 6081012141618Temperature Coefficient(ppm/C)051015CountsHistogram of IREF TC=11.39ppm/C=2.42ppm/C10.22 10.26 10.3 10.34 10.38 10.42 10.46024681012CountsHistogram of Average IREFIREF(A)=10.34A=55.52nAHistograms of IREFwith fixed k1and k2 Average TC
68、of 11.4 ppm/C is achieved3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference56 of 6010-Frequency(Hz)103Current Noise Density(pA/Hz)Noise Spectrum of IREF11.5 pA/HzFsamp=20Hz,NFFT=2500,8X averaging
69、Rectangular Window102101CHOP X,DEM XCHOP O,DEM XCHOP O,DEM OHistogram of IREF Noise-800-600- 400 600 800Noise Current(pA)05000250030003500CHOP X,DEM XCHOP O,DEM XCHOP O,DEM OCountBW=10HzN=20000=38.9pArmsMeasured Noise of IREF Noise floor:11.5 pA/Hz3.1:A PVT-Insensitive Sub-Rang
70、ing Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference57 of 60Comparison TableThis work1JSSC 122ISSCC 173TCAS1 224ESSCIRC 175JSSC 19TI REF200Process(m)0.180.180.180.18 PDSOI0.180.18N/AVDD(V)1.3 to 2.41.2 to 31.3 to 1.80.65 to 1.81.5 to 2.53
71、.3 10%2.5 to 40VLOAD(V)0 to 0.70.3 to 1N/AN/AN/AN/AN/AIREF(A)10.347.816.64n1.0935n15100Supply Currenta(A)43.5 1.8V27.3 1.2V13.8n 1.3V1.09 0.65V35.7n 1.5VN/A100 2.5VTemperature Range(C)-20 to 1250 to 1000 to 110-40 to 85-40 to 120-40 to 85-25 to 85Avg.TC(ppm/C)11.424.9283382823.2b25Line Sensitivity(%
72、/V)0.0360.131.160.213N/A0.0053Load Sensitivity(%/V)0.0180.089N/AN/AN/AN/AN/ARMS Noise(pArms)(Bandwidth)38.9(10Hz)N/AN/AN/AN/AN/A167c(0.1-10Hz)Noise Floor(pA/Hz)11.5N/AN/AN/AN/AN/A20TC TrimmingFixed code(Batch trimmedd)No TrimN/AeFixed codefNo Trim1-pt correlatedtrim at RTN/AXO Required?NoNoNoNoNoYes
73、NoSamples45 from5 corners10 from1 corner10 from1 corner10 from1 corner32 from5 corners380 from4 lots1284 from3 lotsArea(mm2)0.080.1230.0550.00430.017N/AN/Ab TC is measured with a multiplied current of 30mA.f Multi-point trimming is required for different corners.c Reported as 1nApp and it is assumed
74、 as 3 deviation of Gaussian noise.e Trimmed but the method is not available.a Including output current.d Batch includes all 45 samples from 5 corners.3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference58 of
75、60Outline Introduction Key idea Sub-ranging compensation Proposed architectureProposed TC-controllable IR(,T)Circuit implementation Measurement results Conclusion3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conf
76、erence59 of 60Conclusion Proposed Sub-ranging Current ReferenceSmall PVT variation P:Low-process variation in TC(45 chips from 5 corner test with fixed k1 and k2)V:Low-supply&load variation(365ppm/V and 181ppm/V)T:Low-TC in wide-range(11.4ppm/C in-20C to 125C)Low-noise(11.5pA/Hz floor and 38.9pArms
77、in 10Hz BW)Simple implementation(No other reference required)Demo session at 5pm3.1:A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference60 of 60Thank you for listening!3.1:A PVT-Insensitive Sub-Ranging Current Re
78、ference Achieving 11.4ppm/C from-20C to 125C 2024 IEEE International Solid-State Circuits Conference61 of 60Please Scan to Rate This Paper3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE Interna
79、tional Solid-State Circuits Conference1 of 37A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated AgingSining Pan1,Yihang Cheng1,Guohua Wu1,Zhihua Wang1,Kofi A.A.Makinwa2 and Huaqiang Wu11.School of Integrated Circuits
80、,Tsinghua University,China2.Delft University of Technology,Delft,The Netherlands3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference2 of 37MotivationGri
81、ffith,ISSCC Tutorial23Microcontroller Applications3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference3 of 37Integrated Frequency Reference 3.2:A 0.028m
82、m2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference4 of 37Conventional RC Oscillatorn Compact architectureJJn Comparator delay LLRelaxation Oscillator FLL-based Os
83、cillatorn Fout only depends on frontend RCJJn Challenge:Temperature compensationLLVDDVDDC0SWR1VRVC+VCOClock GenClock GenFOUTR2R0VDDVDDC0SWR1VRVCClock GenClock GenFOUTR2R0+Comparator3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccurac
84、y After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference5 of 37n Trim RREF for temperature compensationn Two types of resistors of the opposite TC LL n Only 1st order TC compensation LLTemperature CompensationChen,CICC19VDDVDDC0SWR1VRVC+VCOClock GenClock GenFOUTR2RREF+TC+TC-
85、3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference6 of 37Temperature CompensationPan,JSSC23n Still two types of resistors KKn All negative TC resistor
86、s JJn Only 1st order TC compensation 2800ppm LLVDDVDDC0SWR0VRVC+VCOClock GenClock GenFOUTR1R23.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference7 of 37
87、Pan,JSSC23n Low-TC resistor Easy compensationJJn Aging Bad long-term stabilityLLPolysilicon Resistors and Aging5000ppm Park,JSSC231 week 150C3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE Inte
88、rnational Solid-State Circuits Conference8 of 37Diffusion ResistorsJose,IIRW16 Baking at 200 for 440hrs 2000ppm drift Good long-term stability JJn More difficult TC(1500ppm/)compensation LL2000ppm 101%100%99%0.01Hrs0.1Hrs1Hrs10Hrs100Hrs3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 9
89、00ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference9 of 37Design GoalsnA compact 2nd-order temperature compensation circuit Small chip area Good short-term stability(sub-1000ppm)nAging robust without calibration Goo
90、d long-term stability Preferably only one type of resistor(Diffusion)?3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference10 of 37Proposed Architecturen
91、 Diffusion resistor:current drive for a good PSSn FLL structure+current-based TC compensation How?f RC1IC(T)IR(T)fVDDVDDC0SWR0VRVC+VCOIR(T)Clock GenClock GenIC(T)3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated
92、 Aging 2024 IEEE International Solid-State Circuits Conference11 of 37BJTs for Temperature Compensationn BJT well defined PTAT/CTAT referencesn Aging robust Drift!6mK after 1 year 10ppmn How to achieve a proper TC compensation?Wang,TIE16 obtain TC1 code32MHz32MHz-25C105CFOUTTemp.(3)Adjust f011:0 Int
93、erpolation-targeted frequency32MHz3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference22 of 37Die MicrographP-polyversionN-diffversionP-polyversionP-pol
94、yversionP-polyversionN-diffversionN-diffversionN-diffversion165m190m155m150mRCFront-endRCFront-endTunable biasing circuits,notch filter capsGm,VCOand digitalGm,VCOand digitalTunable biasing circuits,notch filter caps 0.18m standard CMOS 4 N-diff version 4 P-poly version N-diff/P-poly version area:0.
95、028mm2/0.025mm2 N-diff/P-poly version power:131W/139W3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference23 of 37Measured Frequency Inaccuracy TC=10.6pp
96、m/Averaged valueN-diff Inaccuracy:!900ppm(N-diff)TC:10.6ppm/(N-diff),Hysteresis:1000ppm(N-diff)3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference24 of
97、 37Measured Supply Sensitivity2910ppm/VAveraged valueN-diff 3000ppm/V for both versions Effective current driving scheme for N-diff resistors 3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE Int
98、ernational Solid-State Circuits Conference25 of 37Measured Jitter Jitter:18.7ps 600ppm3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference26 of 37Measur
99、ed Allan Deviation 25!C,1s average timeAllan deviation 18.8ppm Allan deviation:18.8ppm 251s average time3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Confer
100、ence27 of 37Measured Start-up BehaviourFreq.drop due to charge sharingSettling time 80sReset releaseSteady state Settling time:80s The worst case scenario (reset gm output to VDD)3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy
101、After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference28 of 37N-diff.Version after Accelerated AgingTC=10.6ppm/Averaged valueAveraged valueTC=18.2ppm/N-diff.Aging Frequency error:!900ppm +1600/-1400ppm Aging condition:1 week 150 at least years of aging RT 3.2:A 0.028mm2 32MH
102、z RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference29 of 37P-poly Version after Accelerated AgingTC=26.7ppm/Averaged valueTC=33.4ppm/Averaged valueP-polyAging Also 2nd or
103、der compensation(Master curve)Frequency error:+2000/-2500ppm -2600/-8100ppm3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference30 of 37Comparison with S
104、tate-of-the-ArtGrleykJSSC22ParkJSSC22JiISSCC22ParkJSSC23WangTCAS-I16PanJSSC23This workTechnology180nm65nm180nm65nm180nm180nm180nmMain resistorP-PolyP-PolyP-PolyP/N-PolyP-PolyP-PolyP-PolyN-DiffCompensation deviceS-PolyN+Diff P+DiffS-Poly N-wellVIA Res.N+DiffN-PolyBJTArea mm20.30.190.070.220.0120.010.
105、0250.028Frequency Hz16M100M2.3M100M12.77M10M32MPower W2201017.614256.285.1139131Energy pJ/cycle13.81.013.31.424.48.514.34.1Temp.range C-4585-4095-40125-4085-30120-45125-40125Temp.coefficient ppm/C a1.32.17.9312.1631 b31.526.710.6Freq.error ppm!90!140+1000/-2000 b!760!9000 b!2800+2000/-2500!900Freq.e
106、rror after aging ppm-!1030 c-3200/-7300 d-2600/-8100 d+1600/-1400 dSupply range V1.621.21.32.01.11.30.61.11.51.81.72.0Supply sensitivity ppm/V40000Jitter ps39.913.395.178.741.418.7Trimming points2322112Number of samples20208a box method b Estimated from the inaccurac
107、y plot c 500hours 125C d 168hours 150C3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference31 of 37Comparison with State-of-the-ArtGrleykJSSC22ParkJSSC22
108、JiISSCC22ParkJSSC23WangTCAS-I16PanJSSC23This workTechnology180nm65nm180nm65nm180nm180nm180nmMain resistorP-PolyP-PolyP-PolyP/N-PolyP-PolyP-PolyP-PolyN-DiffCompensation deviceS-PolyN+Diff P+DiffS-Poly N-wellVIA Res.N+DiffN-PolyBJTArea mm20.30.190.070.220.0120.010.0250.028Frequency Hz16M100M2.3M100M12
109、.77M10M32MPower W2201017.614256.285.1139131Energy pJ/cycle13.81.013.31.424.48.514.34.1Temp.range C-4585-4095-40125-4085-30120-45125-40125Temp.coefficient ppm/C a1.32.17.9312.1631 b31.526.710.6Freq.error ppm!90!140+1000/-2000 b!760!9000 b!2800+2000/-2500!900Freq.error after aging ppm-!1030 c-3200/-73
110、00 d-2600/-8100 d+1600/-1400 dSupply range V1.621.21.32.01.11.30.61.11.51.81.72.0Supply sensitivity ppm/V40000Jitter ps39.913.395.178.741.418.7Trimming points2322112Number of samples20208a box method b Estimated from the inaccuracy plot c 500hours 125C d 168hours 150
111、C3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference32 of 37Comparison with State-of-the-ArtGrleykJSSC22ParkJSSC22JiISSCC22ParkJSSC23WangTCAS-I16PanJSS
112、C23This workTechnology180nm65nm180nm65nm180nm180nm180nmMain resistorP-PolyP-PolyP-PolyP/N-PolyP-PolyP-PolyP-PolyN-DiffCompensation deviceS-PolyN+Diff P+DiffS-Poly N-wellVIA Res.N+DiffN-PolyBJTArea mm20.30.190.070.220.0120.010.0250.028Frequency Hz16M100M2.3M100M12.77M10M32MPower W2201017.614256.285.1
113、139131Energy pJ/cycle13.81.013.31.424.48.514.34.1Temp.range C-4585-4095-40125-4085-30120-45125-40125Temp.coefficient ppm/C a1.32.17.9312.1631 b31.526.710.6Freq.error ppm!90!140+1000/-2000 b!760!9000 b!2800+2000/-2500!900Freq.error after aging ppm-!1030 c-3200/-7300 d-2600/-8100 d+1600/-1400 dSupply
114、range V1.621.21.32.01.11.30.61.11.51.81.72.0Supply sensitivity ppm/V40000Jitter ps39.913.395.178.741.418.7Trimming points2322112Number of samples20208a box method b Estimated from the inaccuracy plot c 500hours 125C d 168hours 150C3.2:A 0.028mm2 32MHz RC Frequency Re
115、ference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference33 of 37Comparison with State-of-the-ArtGrleykJSSC22ParkJSSC22JiISSCC22ParkJSSC23WangTCAS-I16PanJSSC23This workTechnology180nm65nm180nm6
116、5nm180nm180nm180nmMain resistorP-PolyP-PolyP-PolyP/N-PolyP-PolyP-PolyP-PolyN-DiffCompensation deviceS-PolyN+Diff P+DiffS-Poly N-wellVIA Res.N+DiffN-PolyBJTArea mm20.30.190.070.220.0120.010.0250.028Frequency Hz16M100M2.3M100M12.77M10M32MPower W2201017.614256.285.1139131Energy pJ/cycle13.81.013.31.424
117、.48.514.34.1Temp.range C-4585-4095-40125-4085-30120-45125-40125Temp.coefficient ppm/C a1.32.17.9312.1631 b31.526.710.6Freq.error ppm!90!140+1000/-2000 b!760!9000 b!2800+2000/-2500!900Freq.error after aging ppm-!1030 c-3200/-7300 d-2600/-8100 d+1600/-1400 dSupply range V1.621.21.32.01.11.30.61.11.51.
118、81.72.0Supply sensitivity ppm/V40000Jitter ps39.913.395.178.741.418.7Trimming points2322112Number of samples20208a box method b Estimated from the inaccuracy plot c 500hours 125C d 168hours 150C3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Ina
119、ccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference34 of 37Comparison with State-of-the-ArtGrleykJSSC22ParkJSSC22JiISSCC22ParkJSSC23WangTCAS-I16PanJSSC23This workTechnology180nm65nm180nm65nm180nm180nm180nmMain resistorP-Poly
120、P-PolyP-PolyP/N-PolyP-PolyP-PolyP-PolyN-DiffCompensation deviceS-PolyN+Diff P+DiffS-Poly N-wellVIA Res.N+DiffN-PolyBJTArea mm20.30.190.070.220.0120.010.0250.028Frequency Hz16M100M2.3M100M12.77M10M32MPower W2201017.614256.285.1139131Energy pJ/cycle13.81.013.31.424.48.514.34.1Temp.range C-4585-4095-40
121、125-4085-30120-45125-40125Temp.coefficient ppm/C a1.32.17.9312.1631 b31.526.710.6Freq.error ppm!90!140+1000/-2000 b!760!9000 b!2800+2000/-2500!900Freq.error after aging ppm-!1030 c-3200/-7300 d-2600/-8100 d+1600/-1400 dSupply range V1.621.21.32.01.11.30.61.11.51.81.72.0Supply sensitivity ppm/V120083
122、5090003000Jitter ps39.913.395.178.741.418.7Trimming points2322112Number of samples20208a box method b Estimated from the inaccuracy plot c 500hours 125C d 168hours 150C3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm
123、Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference35 of 37Comparison with State-of-the-ArtGrleykJSSC22ParkJSSC22JiISSCC22ParkJSSC23WangTCAS-I16PanJSSC23This workTechnology180nm65nm180nm65nm180nm180nm180nmMain resistorP-PolyP-PolyP-PolyP/N-PolyP-PolyP-PolyP-Pol
124、yN-DiffCompensation deviceS-PolyN+Diff P+DiffS-Poly N-wellVIA Res.N+DiffN-PolyBJTArea mm20.30.190.070.220.0120.010.0250.028Frequency Hz16M100M2.3M100M12.77M10M32MPower W2201017.614256.285.1139131Energy pJ/cycle13.81.013.31.424.48.514.34.1Temp.range C-4585-4095-40125-4085-30120-45125-40125Temp.coeffi
125、cient ppm/C a1.32.17.9312.1631 b31.526.710.6Freq.error ppm!90!140+1000/-2000 b!760!9000 b!2800+2000/-2500!900Freq.error after aging ppm-!1030 c-3200/-7300 d-2600/-8100 d+1600/-1400 dSupply range V1.621.21.32.01.11.30.61.11.51.81.72.0Supply sensitivity ppm/V40000Jitter ps39.913.
126、395.178.741.418.7Trimming points2322112Number of samples20208a box method b Estimated from the inaccuracy plot c 500hours 125C d 168hours 150C3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 20
127、24 IEEE International Solid-State Circuits Conference36 of 37 A compact RC frequency reference with0.028mm2 circuit areaOnly one type of resistor!900ppm variation from-40 to 125 N-diff.resistors show better aging-robustness!1600 ppm after accelerated aging N diff.resistors are better choices for lon
128、g-term stabilityConclusions3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference37 of 37 A compact RC frequency reference with0.028mm2 circuit areaOnly o
129、ne type of resistor!900ppm variation from-40 to 125 N-diff.resistors show better aging-robustness!1600 ppm after accelerated aging N diff.resistors are better choices for long-term stabilityConclusionsThank you for your attention!3.2:A 0.028mm2 32MHz RC Frequency Reference in 0.18m CMOS with 900ppm
130、Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging 2024 IEEE International Solid-State Circuits Conference38 of 37Please Scan to Rate This Paper3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approx
131、imation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference1 of 413.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC CalibrationRui Luo1,Ka-Meng Lei1,Rui P.Martins1,2,Pui-In M
132、ak11University of Macau,Macau,China2Insituto Superior Tcnico/UL,Portugal3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference2 of 41Outl
133、ine Motivation Single-XO Dual-Output(SXDO)Frequency ReferenceSuccessive-approximation(SA)-based RTC calibrationTimer-assisted XO fast startup Measurement Results&Comparison Table Conclusions3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,
134、200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference3 of 41Outline Motivation Single-XO Dual-Output(SXDO)Frequency ReferenceSuccessive-approximation(SA)-based RTC calibrationTimer-assisted XO fast startup Measurement Results&Comparison Table Con
135、clusions3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference4 of 41Multi-Clock of IoT NodeNordic Bluetooth SOC nRF52820Footprint:6.4 mm
136、2Clock configurationLFXOHFXOHFCLKClock controlTo PLLLFCLKClock controlTo RTC32.768kHzFootprint:2.4mm232MHzFootprint:1.92mm2#of crystal 2 PCB area&BoMcost&pin counts MHz XO startup3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Succes
137、sive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference5 of 41Crystal Oscillator vs.On-chip RC OscillatorCrystal oscillatorOn-chip RC oscillatorPowerHighLowExternal deviceCrystal No#of pin2 0 Line sensitivityTC 1 ppm/C 10100 ppm/C3.3:A 0.5V 6.14W Trimming-Fre
138、e Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference6 of 41Challenges and SolutionHF Crystal OscillatorIntegrated RC Oscillator Low-power Always available Poor stab
139、ility Premium stability Duty-cycled Slow startup 3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference7 of 41Challenges and SolutionHF C
140、rystal OscillatorIntegrated RC OscillatorFrequency CalibrationEnergy Injection Low-power Always available Poor stability Premium stability Duty-cycled Slow startup 3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximat
141、ion-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference8 of 412ASSCC2021,T.Lin et al.CNTPLLkRxO32.7 kHz32 MHzfXOfRTC FEETS/MMMDM/PPD/CP/LPFGmENCAL1ISSCC22,J.Jung et al.S-PLLA-FLLFrac.NML-Based Cal.TSUENINJGKDKENCALfRCOPowerCal.ActiveSlp1.2mW83.2W48.2WXO76.8MHzGm32.7kHz32MHz
142、Prior Art 1:Duty-Cycled Calibrated RCOMachine-learning-assisted calibration TC 4ms)&High sleep power(48.2W)3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-S
143、tate Circuits Conference9 of 412ASSCC2021,T.Lin et al.CNTPLLkRxO32.7 kHz32 MHzfXOfRTC FEETS/MMMDM/PPD/CP/LPFGmENCAL1ISSCC22,J.Jung et al.S-PLLA-FLLFrac.NML-Based Cali.TSUENINJGKDKENCALfRCOPowerCal.ActiveSlp1.2mW83.2W48.2WXO76.8MHzGm32.7kHz32MHzPrior Art 2:HFXO-Assisted DCO CalibrationExcellent RTC T
144、C with ultralow power(1.8W)No XO fast start-up,excessive calibration time(10ms)&energy(567nJ)3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits
145、Conference10 of 41Outline Motivation Single-XO Dual-Output(SXDO)FrequencyReferenceSuccessive-approximation(SA)-based RTC calibrationTimer-assisted XO fast startup Measurement Results&Comparison Table Conclusions3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s
146、XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference11 of 41ENXOSA-based FCMfXO(16MHz)XOOn-demandAlways-onFCW13:0fDCO Ctrl.LogicFreq.Multiplier16DCOPEDfDCO ENCALENXOFSMGmDigital CMPECDLLfRTC(1MHz)ENCALProposed SXDO1MHz DCO a
147、lways-on as timerpower&cal.time trade off,DLL design complexityIntermittently calibrated by XO in binary-search approachXO startup accelerated by DCO and frequency multiplier3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-
148、Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference12 of 41CNTPFDST0ST1+ST2fXODig.CompCMPCtrl Logic14NVGfDCOVPG=(ENCAL)?VDD:(-VDD)VPGHigh-VtMPDCOPEDENCALST2ST0-2FCW/16fDCO/401D1D2D3D0CKCALTDCSA-Based RTC Calibration3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual
149、-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference13 of 41CNTPFDST0ST1+ST2fXODig.CompCMPCtrl Logic14NVGfDCOVPG=(ENCAL)?VDD:(-VDD)VPGHigh-VtMPDCOPEDENCALST2ST0-2FCW/16/401D1D2D3D0
150、CKCALTDCDLOUT31 R1Delay CellFCW13:9DLIN1.8m1.6m 127 FCW8:20.3m0.2m B2TB2TB2TFCW1:0To D1-3fDCOSA-Based RTC Calibration:Delay CellThree cap(banks)for process,coarse,and fine tuning3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Success
151、ive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference14 of 41ENCALSTiCKCALfDCOSleepf 250ppm ST0ST1ST2ST1ST2DoneDone1MHzVPG-0.3VVDDRegular calibration(ST1-2)afterwardsVDDCNTPFDST0ST1+ST2fXODig.CompCMPCtrl Logic14NVGfDCOVPG=(ENCAL)?VDD:(-VDD)VPGHigh-VtMPDCOPED
152、ENCALST2ST0-2FCW/16/401CKCALTDCD1D2D3D0fDCOSA-Based RTC Calibration:ST0Counter-based process calibrationOnce after enabling VDD3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE I
153、nternational Solid-State Circuits Conference15 of 41ENCALSTiCKCALfDCOSleepf 250ppm ST0ST1ST2ST1ST2DoneDone1MHzVPGVDD-0.3VVDDRegular calibration(ST1-2)afterwardsCNTPFDST0ST1+ST2fXODig.CompCMPCtrl Logic14NVGfDCOVPG=(ENCAL)?VDD:(-VDD)VPGHigh-VtMPDCOPEDENCALST2ST0-2FCW/16/401CKCALTDCD1D2D3D0fDCOSA-Based
154、 RTC Calibration:ST1PFD&TDC for phase error comparison in 1 DCO cycle3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference16 of 41ENCALS
155、TiCKCALfDCOSleepf 250ppm ST0ST1ST2ST1ST2DoneDone1MHzVPGVDD-0.3VVDDRegular calibration(ST1-2)afterwardsCNTPFDST0ST1+ST2fXODig.CompCMPCtrl Logic14NVGfDCOVPG=(ENCAL)?VDD:(-VDD)VPGHigh-VtMPDCOPEDENCALST2ST0-2FCW/16/401CKCALTDCD1D2D3D0fDCOSA-Based RTC Calibration:DividerPFD&TDC for phase error comparison
156、 in 1 DCO cycleDivider enabled by fDCOto limit phase error within 1 XO cycleDQRfXOU0U1U14f1MHzDQDQQfDCOSU15Main DividerENDIVf1MHzfXOfDCOENDIVfDCO,DIVfDCO,DIVComparison 1Comparison 2DQRDQRDQSReset3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8
157、.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference17 of 41Full calibration(ST0-2)once after enabling VDDENCALSTiCKCALfDCOf 250ppm ST0ST1ST2ST1ST2DoneDone1MHzVPGVDD-0.3VVDDRegular calibration(ST1-2)afterwardsSleepCNTPFDST0ST1+ST2fXODig.Com
158、pCMPCtrl Logic14NVGfDCOVPG=(ENCAL)?VDD:(-VDD)VPGHigh-VtMPDCOPEDENCALST2ST0-2FCW/16/401CKCALTDCD1D2D3D0fDCOSA-Based RTC Calibration:ST2Four CKCALcycles for comparison in ST23.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Ap
159、proximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference18 of 41Full calibration(ST0-2)once after enabling VDDENCALSTiCKCALfDCOf 250ppm ST0ST1ST2ST1ST2DoneDone1MHzVPGVDD-0.3VVDDRegular calibration(ST1-2)afterwardsSleepCNTPFDST0ST1+ST2fXODig.CompCMPCtrl Logic14NVGfDCO
160、VPG=(ENCAL)?VDD:(-VDD)VPGHigh-VtMPDCOPEDENCALST2ST0-2FCW/16/401CKCALTDCD1D2D3D0fDCOSA-Based RTC Calibration:Regular Cal.3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE Internat
161、ional Solid-State Circuits Conference19 of 41Full calibration(ST0-2)once after enabling VDDENCALSTiCKCALfDCOf 250ppm ST0ST1ST2ST1ST2DoneDone1MHzVPGVDD-0.3VVDDRegular calibration(ST1-2)afterwardsSleepCNTPFDST0ST1+ST2fXODig.CompCMPCtrl Logic14NVGfDCOVPG=(ENCAL)?VDD:(-VDD)VPGHigh-VtMPDCOPEDENCALST2ST0-
162、2FCW/16fDCO/401D1D2D3D0CKCALTDCSA-Based RTC Calibration:NVG 20 leakage reduction sleep(1A)3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Con
163、ference20 of 41Outline Motivation Single-XO Dual-Output(SXDO)Frequency ReferenceSuccessive-approximation(SA)-based RTC calibrationTimer-assisted XO fast startup Measurement Results&Comparison Table Conclusions3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO
164、 Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference21 of 41FrequencyMultiplierENXOSA-based FCMfXO(16MHz)XOOn-demandAlways-onFCW13:0fDCO Ctrl.LogicDCOPEDfDCO ENCALENXOFSMGmDigital CMPfRTC(1MHz)ENCALfDCO=1MHz after calibrationP
165、ulse Injection for XO Fast Startup3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference22 of 41FrequencyMultiplierENXOSA-based FCMfXO(16
166、MHz)XOOn-demandAlways-onFCW13:0fDCO Ctrl.LogicDCOPEDfDCO ENCALENXOFSMGmDigital CMPfRTC(1MHz)ENCALfDCO=1MHz after calibrationCombine with 16 freq.multiplier for signal injection to crystalPulse Injection for XO Fast Startup3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with
167、5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference23 of 411 ISSCC22,J.Jung et al.PLLENINJDLLENINJPLL or DLL for freq.Multiplication?PLL-based pulse injectionAuxiliary oscillator required Design complexity Power
168、overhead(tens W)DLL-based pulse injectionNo auxiliary oscillator Low power(10 W)3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference24
169、of 41Start CtrlPDCPMUX0115SetENDLLfDCOdldrefdS3:0VCDLDLLECCNTdECOECO,dTimer-assisted XO fast startup(1/3)3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-Sta
170、te Circuits Conference25 of 41Start CtrlPDCPMUX0115SetENDLLfDCOdldrefdS3:0VCDLDLLECCNTdECO,dECOTimer-assisted XO fast startup(2/3)DLL with 16-unit VCDL16 1-MHz clocks with uniform phase interval(each 62.5 ns)3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO
171、Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference26 of 41Start CtrlPDCPMUX0115SetENDLLfDCOdldrefdS3:0VCDLDLLECCNTECO,ddECO16MHz0115ECO,dECOS3:0 01.2 3 4 5 6 7 8 9 10 111213 14 15 01sd62.5ns To XOTimer-assisted XO fast startu
172、p(3/3)Edge Combiner synthesize 16-MHz pulse,injected pulse to XOd(31.25ns)determined by delay cell(4%variation over Temp.)3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE Intern
173、ational Solid-State Circuits Conference27 of 41Outline Motivation Single-XO Dual-Output(SXDO)FrequencyReferenceSuccessive-approximation(SA)-based RTC calibrationTimer-assisted XO fast startup Measurement Results&Comparison Table Conclusions3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequen
174、cy Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference28 of 41Negative-Voltage GeneratorDigital-Controlled Ring OscillatorFSMDelay-Locked LoopFrequency Calibration ModuleEdge Combiner243m306mXO Cor
175、e(including CL)Chip Micrograph&Power BreakdownDCO(37%)FCM(16%)FSM(14%)EC(6%)XO(14%)DLL(13%)Sleep-mode Power BreakdownOff-state LeakageCalibration Energy BreakdownXO(68.3%)FCM(18.7%)DLL(9.2%)FSM(2.4%)EC(1.4%)65nm CMOS Active area:0.057mm2 VDD:0.5V Crystal loading cap:6pF3.3:A 0.5V 6.14W Trimming-Free
176、 Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference29 of 41Temperature(C)fDCO vs.Temperature w/o&w/i DCO Calibration-40-20020406080100120-4-3-2-101w/o cal.w/i cal.f
177、DCO(%)Intrinsic TC of the RTC:280ppm/C Measurement RTC frequency3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference30 of 41Temperature
178、(C)fDCO vs.Temperature w/o&w/i DCO Calibration-40-20020406080100120-4-3-2-101w/o cal.w/i cal.-4004080120-fDCO(ppm)Temperature(C)fDCO(%)Intrinsic TC of the RTC:280ppm/CTC w/duty-cycled calibration:2.5ppm/CMeasurement RTC frequency3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequ
179、ency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference31 of 41Temperature(C)f after calibration(ppm)fDCO vs.Temperature w/o&w/i DCO Calibration-40-20020406080100120-4-3-2-101w/o cal.w/i cal.-1,00
180、0-5000500 1,0000100200300Occurrences-4004080120-fDCO(ppm)Temperature(C)fDCO Distribution in 1,000 runsfDCO(%)Target regionMeasurement RTC frequency97%f 500ppm after calibration3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,2
181、00s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference32 of 41fDCO(ppm)fDCO vs.Supply Voltage(VDD)VDD(V)0.480.50.520.540.560.580.6-600-600-40-20020406080100 120-600-600Temperature(C)fDCO vs.TemperaturefDCO(ppm)Measuremen
182、t RTC frequencyTC:303ppm against PVT(no manual trimming)3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RTC Calibration 2024 IEEE International Solid-State Circuits Conference33 of 4130s Injectionts(f 2
183、0ppm):120s(96x reduction)ES:5.1nJMeasurement-XO StartupENXOENINJENDLL 100s 30s050100150Time(s)-100-60-20206010020ppmTransient fXO(from 16MHz,ppm)120sfXO3.3:A 0.5V 6.14W Trimming-Free Single-XO Dual-Output Frequency Reference with 5.1nJ,120s XO Startup and 8.1nJ,200s Successive-Approximation-Based RT
184、C Calibration 2024 IEEE International Solid-State Circuits Conference34 of 410.480.50.520.540.560.580.6VDD(V)110120130Start-Up Time vs.Supply Voltage(VDD)-40-20020406080110120130Start-Up Time vs.TemperatureXO Startup Time(s)XO Startup Time(s)Temperature(C)tsvariation 170dB!M.Zhao,JSSC 2020A 14b 98Hz
185、-to-5.9kHz 1.7-to-50.8W BW/Power Scalable Sensor Interface with a Dynamic Bandgap Reference and an Untrimmed Gain Error of 0.26%from-40C to 125C 2024 IEEE International Solid-State Circuits Conference8 of 41Sensor Interface is not only about ADCBGRBufferCLKVINVREF ADCDOUTStaticADCs can be dynamic,BU
186、T its neighbors:Static Bandgap Reference Power Hungry BufferExternal Decoupling CapacitorsLimited ScalabilityIncreased Cost A 14b 98Hz-to-5.9kHz 1.7-to-50.8W BW/Power Scalable Sensor Interface with a Dynamic Bandgap Reference and an Untrimmed Gain Error of 0.26%from-40C to 125C 2024 IEEE Internation
187、al Solid-State Circuits Conference9 of 41Target of This WorkDynamic BGR CLKVIN ADCDOUT ADC with a dynamic BGR No Reference Buffer No External Decaps BW/Power Scalable Good Accuracy:14b resolutionA 14b 98Hz-to-5.9kHz 1.7-to-50.8W BW/Power Scalable Sensor Interface with a Dynamic Bandgap Reference and
188、 an Untrimmed Gain Error of 0.26%from-40C to 125C 2024 IEEE International Solid-State Circuits Conference10 of 41Bandgap Reference(BGR)Precision BGRsG.Ge,JSSC 2011J.-H.Boo,JSSC 2021Low-Power BGRs10ppm/C and VDD0VA 14b 98Hz-to-5.9kHz 1.7-to-50.8W BW/Power Scalable Sensor Interface with a Dynamic Band
189、gap Reference and an Untrimmed Gain Error of 0.26%from-40C to 125C 2024 IEEE International Solid-State Circuits Conference23 of 41On-chip Delay GeneratorAdded CapacitorsC3=C1,C4=C2Cancelled spikes VOP VON C2R2VO R1C1C3VIN C4VIN VDD0VOP VON tVO A 14b 98Hz-to-5.9kHz 1.7-to-50.8W BW/Power Scalable Sens
190、or Interface with a Dynamic Bandgap Reference and an Untrimmed Gain Error of 0.26%from-40C to 125C 2024 IEEE International Solid-State Circuits Conference24 of 41On-chip Delay GeneratorAll dynamic inverter-based comparator:Small delay(84.5dB Gain variation 0.01%A 14b 98Hz-to-5.9kHz 1.7-to-50.8W BW/P
191、ower Scalable Sensor Interface with a Dynamic Bandgap Reference and an Untrimmed Gain Error of 0.26%from-40C to 125C 2024 IEEE International Solid-State Circuits Conference36 of 41Supply VariationSupply:1.1V to 1.4VSNDR Variation 0.2dBGain Variation 30 scalable rangeSNDR 84.5dBUntrimmed gain error 3
192、0 scalable rangeSNDR 84.5dBUntrimmed gain error 0.26%Achieved by:All-dynamic CB BGR in a FIA-based DSMTime-domain TC compensationThank you for your attention!A 14b 98Hz-to-5.9kHz 1.7-to-50.8W BW/Power Scalable Sensor Interface with a Dynamic Bandgap Reference and an Untrimmed Gain Error of 0.26%from
193、-40C to 125C 2024 IEEE International Solid-State Circuits Conference42 of 41Please Scan to Rate This Paper3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference1 of 40A 4mW 45pT/Hz M
194、agnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS TechniquesIppei Akita1and Shunichi Tatematsu21Advanced Industrial Science and Technology(AIST),Tsukuba,Japan2Aichi Steel Corporation,Tokai,Japan3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background
195、 Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference2 of 40Background Highly sensitive magnetic field measurementNeed:gain robustness,digital output,low power,and compactLow noise in geomagnetic field,50T input rangeMagnetoimpedance(MI)element as a
196、sensor headSecurity gate systemsNon-destructive inspectionsBiomagnetic measurements3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference3 of 40Outline MI element as magnetic sensor
197、MI-based magnetometerArchitectureBackground gain calibrationShort-time CDS Implementation and measurement results Conclusions3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference4 o
198、f 40Outline MI element as magnetic sensor MI-based magnetometerArchitectureBackground gain calibrationShort-time CDS Implementation and measurement results Conclusions3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE Intern
199、ational Solid-State Circuits Conference5 of 40MI element as magnetic sensorIexBinTMagnetization vector M Magnetization change on wire surfacePulse Iex&mag.flux density Bin skin effect&M rotationM rotation magnetic flux()change on wire surface Bin BinAmorphous alloy wireK.Mohri,J.Snes.20153.5 A 4mW 4
200、5pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference6 of 40 can be picked up by coilMI element as magnetic sensorK.Mohri,J.Snes.2015Intrinsic sensitivity V/TVin=NtG BinBinTInduced voltage Vin
201、VPickup coil w/N turnsLarger BinVin=GBinIex BinIex3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference7 of 40Outline MI element as magnetic sensor MI-based magnetometerArchitecture
202、Background gain calibrationShort-time CDS Implementation and measurement results Conclusions3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference8 of 40MI-based magnetometer archite
203、ctureSMPLMI driverShiftreg.RDACCalibration logicDetectorDSMPLDoutIfbDLLMUXClock gen.2.56MHzMIECDSTxCDSTx5thorder SC loop filterDctrlVcmp(external)MI elementBin T(1b)Vin,sVinBfb 5th-order modulator w/magnetic neg.feedbackWith MI element in the loopDout Ifb Bfbby RDACWide input rangeStable gain 1/Ifb
204、Sharing coil arch.Sensing(pick up)&magneticfeedback(IfbBfb)Low cost&small size3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference9 of 402 I.Akita,et al.,IEEE JSSC,2022.MI-based ma
205、gnetometer architectureSMPLMI driverShiftreg.RDACCalibration logicDetectorDSMPLDoutIfbDLLMUXClock gen.2.56MHzMIECDSTxCDSTx5thorder SC loop filterDctrlVcmp(external)MI element(1b)Vin,sVin DLL-based clock gen.2Miximizes MI sensitivity G higher loop gain(low noise)Synchronizes MIE and SMPLSMPLVinMIEVin
206、,sMaximize G3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference10 of 40MI-based magnetometer architectureSMPLMI driverDoShiftreg.RDACCalibration logicDetectorDSMPLDoutIfbDLLMUXClo
207、ck gen.2.56MHzMIECDSTxCDSTx5thorder SC loop filterDctrlVcmp(external)MI element(1b)Vin,sVin 12-tap FIR RDAC forminimizing VinswingReduces non-linearityEnhances tolerance to jitter onpeak sampling clock,SMPL 212-tapFIR RDAC2 I.Akita,et al.,IEEE JSSC,2022.3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magne
208、tometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference11 of 40MI-based magnetometer architectureSMPLMI driverDoShiftreg.RDACCalibration logicDetectorDSMPLDoutDLLMUXClock gen.2.56MHzMIECDSTxCDSTx5thorder SC loop filterDctrlVcmpSh
209、ort-time CDS(ST-CDS)(external)MI element(1b)Vin,sVin Automatic gain calibrationBackground operation Corrects gain by monitoring&tuning Ifb Short-time CDS(ST-CDS)Lower powerGain robustnessGain calibration loopIfb3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration an
210、d Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference12 of 40Outline MI element as magnetic sensor MI-based magnetometerArchitectureBackground gain calibrationShort-time CDS Implementation and measurement results Conclusions3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magne
211、tometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference13 of 40Background gain calibration loopReplicaVinpDctrlIfbRpRDACDo0Do0Do0Do0Do11:0(external)Iref(from shift reg.)+Cal.logicDetector(comparator)VrefVcmpRURU2 cells12 cellsGai
212、n calibration loop Feedback current Ifbby RDACRDAC:12 cells 13 levels of IfbVDDvariation&Coils parasitic resistor Rp Ifb(gain)changeTunable unit resistor RUin each cell adjustment of Ifbby loop CalibrationMonitors Vinp(indirect monitoring of Ifb)Updates RUuntil Vinp VrefReference voltage:VrefVDDVDD3
213、.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference14 of 40Background gain calibration loopReplicaDctrlIfbRpRDACDo0Do0Do0Do0Do11:0(external)Iref(from shift reg.)+Cal.logicDetector(
214、comparator)VrefVcmpRURU2 cells12 cellsVinp Vreffrom replica2 cells and IrefSteady state:Vinp Vref Ifb Iref3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference15 of 40Background gai
215、n calibration loopReplicaDctrlIfbRpRDACDo0Do0Do0Do0Do11:0(external)Iref(from shift reg.)+Cal.logicDetector(comparator)VrefVcmpRURU2 cells12 cellsVinp Vreffrom replica2 cells and IrefSteady state:Vinp Vref Ifb Iref RUupdate ruleSame situation between replica andRDAC sidesThe number of“High-state bits
216、”in Doshould be 2 larger than”Low-stateones”7 highs&5 lows Do=2(minimum positive value)3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference16 of 40Background gain calibration loopR
217、eplicaVinpDctrlIfbRpRDACDo0Do0Do0Do0Do11:0(external)Iref(from shift reg.)+Cal.logicDetector(comparator)VrefVcmpFor monitoring Do=“2”RURU2 cells12 cells Vreffrom replica2 cells and IrefSteady state:Vinp Vref Ifb Iref RUupdate ruleSame situation between replica andRDAC sidesThe number of“High-state bi
218、ts”in Doshould be 2 larger than”Low-stateones”By monitoring Doin the calibration logic3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference17 of 40Calibration processReplicaVinpDctr
219、lIfbRpRDACDo0Do0Do0Do0Do11:0(external)Iref(from shift reg.)+Cal.logicDetector(comparator)VrefVcmpRURU2 cells12 cells(1)DoDctrldownVcmpIrefIfbVDD Ex)when VDDdrops(2)(3)(3)downdowndownup(5)(4)(9)(6)(7)(8)VDDdrops Ifbalso does&Vinpgoes upIf Do=2 and VinpVref,the loopupdates RU(Ifb)3.5 A 4mW 45pT/Hz Mag
220、netoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference18 of 40Calibration processReplicaVinpDctrlIfbRpRDACDo0Do0Do0Do0Do11:0(external)Iref(from shift reg.)+Cal.logicDetector(comparator)VrefVcmpRURU2 cell
221、s12 cells(1)DoDctrldownVcmpIrefIfbVDD Ex)when VDDdrops(2)(3)(3)downdowndownup(5)(4)(9)(6)(7)(8)If Do 2,no RUupdate3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference19 of 40Calibr
222、ation processReplicaVinpDctrlIfbRpRDACDo0Do0Do0Do0Do11:0(external)Iref(from shift reg.)+Cal.logicDetector(comparator)VrefVcmpRURU2 cells12 cells(1)DoDctrldownVcmpIrefIfbVDD Ex)when VDDdrops(2)(3)(3)downdowndownup(5)(4)(9)(6)(7)(8)RUonly when IfbIref&Do=2,Dctrl3.5 A 4mW 45pT/Hz Magnetoimpedance-based
223、 Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference21 of 40Outline MI element as magnetic sensor MI-based magnetometerArchitectureBackground gain calibrationShort-time CDS Implementation and measurement results Conclusi
224、ons3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference22 of 40Duty-cycled negative feedback1ststage SC integratorDoutto latter stagesSMPLCDSTx0CDSSMPLMIERpSMPLDoRUENENENMIETxRUDoT
225、xTxVin Low-power operationRDAC(Ifb)is ON only when EN=HVin RDAC needs larger powerIfb:OFF3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference23 of 40Duty-cycled negative feedback C
226、oils parasitice resistor Rpdegrades magnetic negative feedback effect worse gain robustness 21ststage SC integratorDoutto latter stagesSMPLCDSTx0CDSSMPLMIERpSMPLDoRUENENENMIETxRUDoTxTxVinVin,sRpIfb+(undesired term)(desired)Vin2 I.Akita,et al.,IEEE JSSC,2022.3.5 A 4mW 45pT/Hz Magnetoimpedance-based M
227、agnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference24 of 40Short-time CDS(ST-CDS)Cross-coupled configurationEnables CDS operation in short time lower duty ratio for Ifb1ststage SC integratorDoutto latter stagesSMPLCDSTx0C
228、DSSMPLMIERpSMPLDoRUENENENMIETxRUDoTxVinTxVinTwo sampling process3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference25 of 40TxShort-time CDS(ST-CDS)Cross-coupled configurationEnabl
229、es CDS operation in short time lower duty ratio for Ifb1ststage SC integratorDoutto latter stagesSMPLTx0CDSSMPLMIERpRpIfbRpIfb+SMPLDoRUENENENMIETxRUDoTxCDSVinSampling only undesired RpIfbVin3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS tech
230、niques 2024 IEEE International Solid-State Circuits Conference26 of 40TxShort-time CDS(ST-CDS)Cross-coupled configurationEnables CDS operation in short time lower duty ratio for Ifb1ststage SC integratorDoutto latter stagesSMPLTx0CDSSMPLMIERpRpIfbRpIfb+SMPLDoRUENENENMIETxRUDoTxVinVin,sRpIfb+(undesir
231、ed)(desired)CDS+Sampling desired signal with undesired RpIfbVin3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference27 of 40Vin,sShort-time CDS(ST-CDS)Cross-coupled configurationEna
232、bles CDS operation in short time lower duty ratio for Ifb1ststage SC integratorDoutto latter stagesSMPLTx0CDSSMPLMIERpRpIfbRpIfb+SMPLDoRUENENENMIETxRUDoVin(desired)CDS+Tx()RpIfbVin,s(desired)Q transfer phase with cross coupledRpIfbcancelledRpIfb+(undesired)TxVin3.5 A 4mW 45pT/Hz Magnetoimpedance-bas
233、ed Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference28 of 40Outline MI element as magnetic sensor MI-based magnetometerArchitectureBackground gain calibrationShort-time CDS Implementation and measurement results Conclu
234、sions3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference29 of 40Chip microphotograph and test board180nm CMOSMI elementMI element die6mm x 0.6mmHinAFE IC3.5 A 4mW 45pT/Hz Magnetoi
235、mpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference30 of 40Measurement setupMagnetic shield box(3 layered permalloy)Helmholtz coilPC for measurement controlClock&signal generatorDUT&Ref.magnetometerOscillo
236、scopeBipolar amplifierIref(500A)SPI&logic analyzer3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference31 of 40DC curve and noise PSDNoise PSD dBLinearity error%Input,BinTDigital ou
237、tput,Dout80T input range+0.6%/-0.57%BW:10kHz45pT/Hz noise floor10 100 1k 10k 100kFrequency Hz65536pt FFT 80T input range&45pT/Hz in 10kHz Bw 82dB DR6.1kT-13.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Soli
238、d-State Circuits Conference32 of 40Gain for VDDvariationGain calibration:OFFGain calibration:ON10 samples10 samples6.01kT-1 6.14kT-1Bin-to-Doutgain T-17.0k6.5k6.0k5.5k5.0kVDDVVDDV65%relative gain errorreduction on average3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Cali
239、bration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference33 of 40Gain for MI sensitivity variationPeak sampling delay10 samplesw/o ST-CDSw/ST-CDSRelative gain error%At DSMPL=5(optimum)Emulation of MIs intrinsicsensitivity variation Relative gain error when normali
240、zed at DSMPL=580%slope reductionaround DSMPL=53.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference34 of 40Performance summary*1:Estimated from DR and input range*2:At Bin=0T*3:Incl
241、uding excitation power for FG*4:*5:Die area including sensor head*6:Module scaleFoM 6=(R/N)2 BwPowerR:input range TN:noise Trms3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference3
242、5 of 40Performance summary*1:Estimated from DR and input range*2:At Bin=0T*3:Including excitation power for FG*4:*5:Die area including sensor head*6:Module scaleFoM 6=(R/N)2 BwPowerR:input range TN:noise Trms3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and S
243、hort-time CDS techniques 2024 IEEE International Solid-State Circuits Conference36 of 40Performance summary*1:Estimated from DR and input range*2:At Bin=0T*3:Including excitation power for FG*4:*5:Die area including sensor head*6:Module scaleFoM 6=(R/N)2 BwPowerR:input range TN:noise Trms3.5 A 4mW 4
244、5pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference37 of 40Performance summary*1:Estimated from DR and input range*2:At Bin=0T*3:Including excitation power for FG*4:*5:Die area including sen
245、sor head*6:Module scaleFoM 6=(R/N)2 BwPowerR:input range TN:noise Trms3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference38 of 40Outline MI element as magnetic sensor MI-based mag
246、netometerArchitectureBackground gain calibrationShort-time CDS Implementation and measurement results Conclusions3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference39 of 40Conclus
247、ions Power-efficient magnetometer with digital outputMI-based architecture with magnetic negative feedbackBackground gain calibration Resistor tuning in RDAC Gain robustness 65%gain error reduction for VDDvariationST-CDS Duty-cycled feedback current low power 80%gain sensitivity improvement to loop
248、gain variation3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference40 of 40Acknowledgement T.Fukunaga at AIST for help of layout design andmeasurements T.Kawano,H.Ishii,Y.Shimizu,S.
249、Itabuchi,Y.Okita,Y.Iwanaga at Aichi Steel Co.,and K.Hioki atAIST for valuable discussion.3.5 A 4mW 45pT/Hz Magnetoimpedance-based Magnetometer with Background Gain Calibration and Short-time CDS techniques 2024 IEEE International Solid-State Circuits Conference41 of 40Please Scan to Rate This Paper3
250、.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference1 of 60An Amplifier-less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical
251、BiosensingMuhammad Abrar Akram1,Aida Aberra1,2,Soon-Jae Kweon3,Sohmyung Ha1,21New York University Abu Dhabi,Abu Dhabi,UAE2New York University,New York,NY,USA3The Catholic University of Korea,Bucheon,Korea3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range
252、for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference2 of 60Outline Background and Motivation Amplifier-less CMOS PotentiostatCircuit ArchitectureOverall Architecture and Operation Implementation and Measurement Results Conclusion3.6:An Amplifier-Less CMOS Potentiost
253、at IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference3 of 60Outline Background and Motivation Amplifier-less CMOS PotentiostatCircuit ArchitectureOverall Architecture and Operation Implementation and Measurem
254、ent Results Conclusion3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference4 of 60Motivation:Electrochemical Biosensors Detect and quantify biological molecules by convert
255、ing biological response to electrical signal1 E.Kim et al.,Trends in Biotechnology,Jan.2023Advantages High sensitivity and specificity Rapid result Portability and miniaturization Multiplexing capabilityIn Vitro DiagnosisWearable Biosensors MouthEyesSkin SwabSalivaBloodUrineContinuous Monitoring Bio
256、sensors3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference5 of 6055404570140Example:Implantable Glucose Biosensor Real-time glucose level monitoring without f
257、requent blooddraws or finger pricks Can be measured every few minutes to observe the trendGlucose Concentration (mg/dl)Time(min)3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits
258、Conference6 of 6055404570140What Data Does CGM Provide?Glucose exposure Glucose variabilityRequirements High linearity High precision of measurement is not necessary High SNDR not necessary2 J.Aymerich et al.,IEEE Access,Apr.2020Glucose Concentration (mg/dl)Time(min)3.6:An Amplifier-Less
259、CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference7 of 60ChronoamperometryVWEVCEVREReference Electrode(RE)Working Electrode(WE)Counter Electrode(CE)3.6:An Amplifier-Less CMOS Potentiostat IC
260、 Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference8 of 60ChronoamperometryVWEVCEVREIRE=0 Sets the common potential of the solutionReference Electrode(RE)Working Electrode(WE)Counter Electrode(CE)3.6:An Amplifie
261、r-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference9 of 60ChronoamperometryVWEVCEVREMaintains the potential difference between WE and RE+VWE-REReference Electrode(RE)Working Electrode(
262、WE)Counter Electrode(CE)PotentiostatIRE=0 Sets the common potential of the solution3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference10 of 60ChronoamperometryVWEVCEVRE+
263、VWE-REMeasures current flow from WE to CE Current information about chemical reactionIINReference Electrode(RE)Working Electrode(WE)Counter Electrode(CE)Maintains the potential difference between WE and RE PotentiostatIRE=0 Sets the common potential of the solution3.6:An Amplifier-Less CMOS Potentio
264、stat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference11 of 60RFBIINVWE_REFVRE_REFVWEVCEVOUTIRE=0VREConventional Potentiostat IC3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5
265、dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference12 of 60Potentiostat IC Requirements Low power as sub-WRFBIINVWE_REFVRE_REFVWEVCEVOUTIRE=0VRE3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Elec
266、trochemical Biosensing 2024 IEEE International Solid-State Circuits Conference13 of 60Potentiostat IC Requirements Low power as sub-W Dynamic range 120 dB for range of applicationsSingle-molecule detection nA rangeGlucose detection A rangeRFBIINVWE_REFVRE_REFVWEVCEVOUTIRE=0VRE3.6:An Amplifier-Less C
267、MOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference14 of 60 Low power as sub-W Dynamic range 120 dB for wide applicationsSingle-molecule detection nA rangeGlucose detection A range Small form
268、factorPotentiostat IC Requirements3 https:/phys.org/news/2014-11-medical-lab-home.htmlRFBIINVWE_REFVRE_REFVWEVCEVOUTIRE=0VRE3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conf
269、erence15 of 60DOUTADCRFBIINVWE_REFVRE_REFVWEVCEIRE=0VREPrior Potentiostats:Using TIA with R Feedback5 K.Al Mamun et al.,TBioCAS,Aug.20164 E.Kang et al.,JSSC,Dec.20206 Q.Lin et al.,ISSCC,Feb.2023VWE_RE=VWE VRE3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Ra
270、nge for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference16 of 60DOUTADCRFBIINVWE_REFVRE_REFVWEVCEIRE=0VREPrior Potentiostats:Using TIA with R Feedback ADC:digitizes VOUTinto DOUTSimple straightforward implementation!TIA:converts IINto VOUTthrough RFBVWE_RE=VWE VRE3.
271、6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference17 of 60DOUTADCRFBIINVWE_REFVRE_REFVWEVCEVREPrior Potentiostats:Using TIA with R FeedbackTIA gain of 100 M G range for b
272、iomedical applicationsHuge RFBDynamic range(DR)limited by,=/3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference18 of 60IINcurrentIINITIATIA current requirementsAt low II
273、N:High ITIArequired for low noisePrior Potentiostats:Using TIA with R FeedbackDOUTADCRFBIINVWE_REFVRE_REFVWEVCEVRETIA3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference1
274、9 of 60IINcurrentIINITIATIA current requirementsAt low IIN:High ITIArequired for low noiseAt high IIN:High ITIArequired for driving highcurrentPrior Potentiostats:Using TIA with R FeedbackDOUTADCRFBIINVWE_REFVRE_REFVWEVCEVRETIA3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over
275、 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference20 of 60IINcurrentIINITIATIA current requirementsAt low IIN:High ITIArequired for low noiseAt high IIN:High ITIArequired for driving highcurrentPrior Potentiostats:Using TIA with R FeedbackIn
276、put referred noise dependent on RFB2=4/DOUTADCRFBIINVWE_REFVRE_REFVWEVCEVRE3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference21 of 60RFBIINVWE_REFVRE_REFDOUTADCCFBSRSTV
277、WEVCEVREPrior PotentiostatsReplacing RFBwith CFBand SRSTLower noise than R-TIATIA based:C-TIA 7 M.Nazari et al.,Symp.VLSI,Jun.20148 C.Hsu et al.,TBioCAS,Oct.20153.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE In
278、ternational Solid-State Circuits Conference22 of 60Prior PotentiostatsReplacing RFBwith CFBand SRSTLower noise than R-TIATIA based:C-TIA DR is limited by VDD,CFB and TP,=/VDD0resetresettamplifyingTPIncreasing IINLarge CFBneeded for higher IIN9 C.-L.Hsu et al.,ISSC,Feb.2018RFBIINVWE_REFVRE_REFDOUTADC
279、CFBSRSTVWEVCEVRE3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference23 of 60RFBIINVWE_REFVRE_REFDOUTADCCFBSRSTVWEVCEVREPrior PotentiostatsTIA based:C-TIA Explicit ADC and
280、 control amplifierOverhead area and power consumption3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference24 of 60IINIMIRVRE_REF1:MCounterDOUTI FFOUTIAMPVWEVCEVREPrior Pot
281、entiostats:Open-loop I-F Converter Direct current-to-frequency conversionCurrent mirroring and current conversionIIN:Mirrored and converted to frequencyAvoids using TIA,large passives,or explicit ADC!10 H.Jiang et al.,CICC,Apr.201811 T.Chou et al.,TBioCAS,Aug.2023VWE_RE=VWE VRE 3.6:An Amplifier-Less
282、 CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference25 of 60IINIMIRVRE_REF1:MCounterDOUTI FFOUTIAMPVWEVCEVREPrior Potentiostats:Open-loop I-F Converter DR vs power consumption(4 10 W)10 H.Jia
283、ng et al.,CICC,Apr.201811 T.Chou et al.,TBioCAS,Aug.20233.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference26 of 60IINIMIRVRE_REF1:MCounterDOUTI FFOUTIAMPVWEVCEVREIAMPIM
284、IRFOUTIMIRPrior Potentiostats:Open-loop I-F Converter Non-Linearity3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference27 of 60IINIMIRVRE_REF1:MCounterDOUTI FFOUTIAMPVWEV
285、CEVREPrior Potentiostats:Open-loop I-F Converter IAMPIMIRFOUTIMIRNon-Linearity3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference28 of 60IINVRE_REFCounterI FFOUT+IDAC1:M
286、Control LogicsDACTDCVWEVCEVREPrior Potentiostats:Open-loop I-F Converter Non-linearities of CM and I-F stages are suppressed12 S.Lu et al.,TBioCAS,Apr.202114 S.Lu et al.,ISSCC,Feb.202113 S.Yu et al.,TBioCAS,Aug.20233.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dyn
287、amic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference29 of 60DR vs power consumption(9 49 W)Complex structurePrior Potentiostats:Closed loop I-F Converter 12 S.-Y.Lu et al.,TBioCAS,Apr.202114 S.-Y.Lu et al.,ISSCC,Feb.202113 S.-Y.Lu et al.,TBioCAS,Aug.2023I
288、INVRE_REFCounterI FFOUT+IDAC1:MControl LogicsDACTDCVWEVCEVRE3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference30 of 60Outline Background and Motivation Amplifier-less C
289、MOS PotentiostatCircuit ArchitectureOverall Architecture and Operation Implementation and Measurement Results Conclusion3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conferen
290、ce31 of 60FSCounterUD1VDDDOUTVRE_REFVWEVCEVREProposed Potentiostat:Circuit Architecture Synchronous Digital-LDO-like structurePrecise voltage-current regulationVWE_RE=VWE VRE IIN3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosen
291、sing 2024 IEEE International Solid-State Circuits Conference32 of 60FSCounterUD1VDDDOUTVRE_REFVWEVCEVRE Clocked ComparatorVRE VRE_REF:UD1=0VRE VRE_REF:UD1=0VRE VRE_REF:UD1=1 Counter&CSUD1=0:Up-counting,IIN UD1=1:Down-counting,IIN Proposed Potentiostat:Circuit ArchitectureIIN Synchronous Digital LDOP
292、recise voltage-current regulation3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference34 of 60FSCounterUD1VDDDOUTVRE_REFVWEVCEVREVRE_REFtimeUp CountingDN UPDNUPDNVREIINFSU
293、D1DOUT Start-up StateVREtracks VRE_REFwhile supplying IINStart-upProposed Potentiostat:Circuit ArchitectureIIN3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference35 of 60
294、FSCounterUD1VDDDOUTVRE_REFVWEVCEVREtimeUPUp CountingDN UPDNUPDNVREIINFSUD1timeDOUTVRE_REFSteady-State Steady-StateVRE=VRE_REFand LSB toggles with UD1DOUTof current source IIN measurementProposed Potentiostat:Circuit ArchitectureIINStart-up3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Po
295、wer all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference36 of 60FSCounterUD1VDDDOUTVRE_REFVWEVCEVREProposed Potentiostat:Circuit ArchitectureIINLow power consumptionNo amplifier High linearityDigital regulation loop Wide dynamic rangeC
296、urrent source design3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference37 of 60Overall Circuit Diagram Dynamic-latch comparators Digital-loop filters(DLFs)Current sourci
297、ng/sinking DACsDLFFSUD2SW9:0VBNHVBNLRWERCEREVWEVREVCECurrent-Steering DACSwitch BuffersINMVRE_REFCEVDD3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference38 of 60FSFSFSVN
298、VPONOPXYTunning bitsONOPUDOutput LatchOffset cancellationOffset cancellationTunning bitsLatch-based Dynamic Comparator Dynamic comparator Output latch3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International
299、 Solid-State Circuits Conference39 of 60 Wide current range using binary-weighted sizing Current-sinking DACCurrent-Steering DACsM1Iu/8Iu/4Iu/2Iu1232Iu49VBNLVBNH64IuVCE3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024
300、IEEE International Solid-State Circuits Conference40 of 60VRE_REFVWE_REFFSDOUT_WECounterFSCounterDOUT_WEBGUD2UD1FSCounterUD3VWEVCEVREVWEBGVWEBG_REFProposed Potentiostat:Differential Sensing Digital regulation loop supplies regulated VWE and VWEBG3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3
301、.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference41 of 60VRE_REFVWE_REFFSDOUT_WECounterFSCounterDOUT_WEBGUD2UD1FSCounterUD3VWEVCEVREVWEBGVWEBG_REFProposed Potentiostat:Differential Sensing Measures IINand IINBGseparatelyI
302、INBGIINISINK3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference42 of 60VRE_REFVWE_REFFSDOUT_WECounterFSCounterDOUT_WEBGUD2UD1FSCounterUD3VWEVCEVREVWEBGVWEBG_REFProposed
303、Potentiostat:Differential Sensing Voltage-current regulation feedback loops:precise current matching,high linearity,wide DR,and small power consumptionIINBGIINISINKVWE_RE=VWE VRE VWEBG_RE=VWE BG VRE 3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for E
304、lectrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference43 of 60Outline Background and Motivation Amplifier-less CMOS PotentiostatCircuit ArchitectureOverall Architecture and Operation Implementation and Measurement Results Conclusion3.6:An Amplifier-Less CMOS Potentiostat I
305、C Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circuits Conference44 of 60Chip and Layout Photo 0.18-m CMOS process Overall core area:0.066 mm2single-ended 0.266 mm2differential336m300mMain SensingLoop336m300mBKG SensingLoop3
306、00m215mCE RegulationLoopPMOS IDADLFMOS IDAC0.1 mm20.1 mm20.066 mm2 Operating RangesVDD:1.0 V 1.8 VFS:100 Hz 100 MHzIIN:80 pA 240 A 3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circui
307、ts Conference45 of 60Transient Response VDD=1.2 V,VREF_WE=1.1 V,VREF_RE=0.6 V,FS=1 kHz,IIN=1 A Reset StateSteady StateVWEVRE1.1V0.6VStart-up3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-Sta
308、te Circuits Conference46 of 60Transient ResponseReset StateSteady StateVWEVRE1.1V0.6VStart-up0.9950.987Peak SNDR dBN/A68.3N/AN/A45453.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE International Solid-State Circu
309、its Conference58 of 60Conclusion A digitally controlled amplifier-less potentiostat for electrochemicalbiosensing applications is proposed Implemented usingFully scalable design with clocked comparators and counters-based digitalcontrol to reduce power consumptionVoltage-current regulation feedback
310、loops to increase linearity and DRCurrent-sourcing and sinking IDACs Result:An amplifier-less potentiostatwith 129.5-dB DR,and 3.72-nW power consumption3.6:An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for Electrochemical Biosensing 2024 IEEE Internation
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321、mpensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference1 of 42A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoMNandor G.Toth1,Kofi A
322、.A.Makinwa11Delft University of Technology,Delft,The Netherlands A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference2 of 42CMOS Temperature Sensors BJT-based T-sensors:Accurate after 1-
323、pt.trim Moderate energy efficiency FoM=Resolution2Energy/ConversionRelative Inacc.=Inacc/Temperature RangeK.A.A.Makinwa,Smart Temperature Sensor Survey”A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State C
324、ircuits Conference3 of 42 VBE=(kT/q)ln(p)PTAT VBE=(kT/q)ln(IC/IS)CTAT VREF=VBE+VBE constantBJT-Based Sensor:Operating PrincipleA-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference4 of 42
325、 Temperature-linearoutputNon-integer BJT-Based Sensor:Operating PrincipleA-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference5 of 42 Digitize X=VBE/VBE lin=/(+X)in digital domain VBE is
326、smallOn-chip amp.factor kBJT-Based Sensor:Operating PrincipleYousefzadeh et al.,JSSC17A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference6 of 42Voltage Readout Digitize w/-Modulator Swi
327、tched-Capacitor readoutDirectly integrate voltages k set by C-ratio kT/C noise Yousefzadeh et al.,JSSC17A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference7 of 42Current ReadoutR1&R2gen
328、erate IPTAT&ICTATBalance using I-DACCT current readout:No kT/C noise k set by R-ratio Pertijs et al.,ISSCC03A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference8 of 42PNP Front-End Estab
329、lish VBE-loopForce VBEover resistor Mirror emitter currentIPTATdirectly mirrored to ADC A1in loopNoise A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference9 of 42 PNP-based Front-EndSimp
330、le 0.1C Inacc.(-55C-125C)Opamp noise FoM=850fJK2Toth et al.,ISSCC23Prior Art(1/2)A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference10 of 42NPN Front-End No opamp in VBE-loopBetter nois
331、e Mirror collector currentIADC IPTATA-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference11 of 42Prior Art(2/2)NPN-based Front-EndNo opamp noise FoM=190fJK2-limited accuracy Shalmany et a
332、l.,ISSCC20A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference12 of 42Fixing the-Issue Emitter area ratio r Diode-connected NPNVBE=(kT/q)ln(rIC2/IC1)2IBsubtracted from IC2-dependent erro
333、r!A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-State Circuits Conference13 of 42Fixing the-Issue Buffer 2IBIC1=IC2VBEis-independent IC1=IPTAT-IB-error in IADC!A-Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy from-55C to 125C and a 200fJK2Resolution FoM 2024 IEEE International Solid-Stat