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1、ISSCC 2024SESSION 10Frequency Synthesis10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4d
2、B FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference1 1 of of 4747An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and-252.4dB FoMM.Rossoni*,S.M.Dartizio*,F.Tesol
3、in,G.Castoro,R.DellOrto,C.Samori,A.L.Lacaitaand S.Levantino*Equally-Credited Authors(ECAs)Politecnico di Milano,Milan,Italy10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving A
4、chieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference2 2 of of 4747 DTC-Based Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Re
5、verse-Concavity Variable-Slope DTC-Adaptive Concavity Zeroing algorithm Implementation and Measurements Conclusions Outline10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving A
6、chieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference3 3 of of 4747 DTC-Based Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Re
7、verse-Concavity Variable-Slope DTC-Adaptive Concavity Zeroing algorithm Implementation and Measurements Conclusions Outline10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving A
8、chieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference4 4 of of 4747Challenges in Modern High Data-Rate TransceiversHigh order modulations to increas
9、e data-rate LO with low phase noise and low spursHigh output frequency accuracy LO with high frequency resolution10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 5
10、7.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference5 5 of of 4747A Fractional-N PLL where a DTC is used to remove the quantization error at the phase detect
11、or input can achieve both low phase noise and high frequency resolution.DTC-based Fractional-N PLL10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms In
12、tegrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference6 6 of of 4747DTC noise and nonlinearity cause a degradation of LOOUTphase noise,leading to increased in-band noise and
13、fractional spurs in the PLL output spectrum.DTC-based Fractional-N PLL10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms In
14、tegrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference7 7 of of 4747 DTC-Based Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Reverse-Concavity Variable-Slope DTC-Adaptive Concavity
15、 Zeroing algorithm Implementation and Measurements Conclusions Outline10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms In
16、tegrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference8 8 of of 4747Prior-Art:Variable-Slope(VS)DTC(1 of 3)The Variable-Slope DTC(VS-DTC)is one of the most common DTC topology thanks to its simple archi
17、tecture and competitive power-jitter trade-off.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252
18、.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference9 9 of of 4747The linearity in a VS-DTC is limited by the slope-dependent propagation delay T2of the output buffer,which causes an INL with a downward concavity shape.Prio
19、r-Art:Variable-Slope(VS)DTC(2 of 3)Ru et al.JSSC1510.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-
20、252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference1010 of of 4747To reduce this effect,the INL is typically improved by adding a fixed capacitance CFIXto reduce the slope variation.Prior-Art:Variable-Slope(VS)DTC(3 of
21、3)Wu et al.JSSC1910.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024
22、IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference1111 of of 4747However,the addition of CFIXcauses an increase of VS-DTC power consumption and phase noise due to higher capacitive load and slower charging slope.Variable-Slope(VS)DTC:FoM-Linearity tra
23、de-off(1 of 2)Santiccioli et al.EL1710.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB F
24、oMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference1212 of of 4747This limits the achievable power-jitter FoM in a VS-DTC,thus introducing a power-jitter vs linearity trade-off.Variable-Slope(VS)DTC:FoM-Linearity trade-off(2 of 2)10.
25、110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE Internatio
26、nal SolidInternational Solid-State Circuits ConferenceState Circuits Conference1313 of of 4747 DTC-Based Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Reverse-Concavity Variable-Slope DTC-Adaptive Concavity Zeroing algorithm Implementation and Measurements Conclusions Outline10
27、.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE Internati
28、onal SolidInternational Solid-State Circuits ConferenceState Circuits Conference1414 of of 4747Reverse-Concavity Variable-Slope(RCVS)DTC:ConceptIn the RCVS-DTC,the addition of a resistor RUin each capacitor cell causes the propagation delay T1of the first stage to become nonlinear.10.110.1:An An 8.7
29、58.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidIntern
30、ational Solid-State Circuits ConferenceState Circuits Conference1515 of of 4747Reverse-Concavity Working Principle(1 of 2)The first stage load impedance Z1shows a DTCcodedependent value,which causes a DTCcodedependent LSB T1,LSBof the first stage.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N
31、 Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits Confer
32、enceState Circuits Conference1616 of of 4747Reverse-Concavity Working Principle(2 of 2)T1,LSBbecomes an increasing monotonic function of the DTCcode,which translates in a T1delay with an upward concavity INL.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PL
33、L with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference1717 of of
34、 4747Reverse-Concavity Variable-Slope(RCVS)DTC(1 of 2)Combined with the T2downward concavity INL,the RCVS-DTC INL shows an overall concavity depending on the sum of the two.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity Variable
35、Concavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference1818 of of 4747Reverse-Concavity Variable-Slo
36、pe(RCVS)DTC(2 of 2)Changing the value of RU,the RCVS-DTC INL changes from an upward to downward concavity,resulting in a significant DTCINLreduction if proper value of RUis chosen.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity V
37、ariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference1919 of of 4747VS-DTC vs RCVS-DTCConve
38、ntional Variable-Slope DTCReverse-Concavity Variable-Slope DTCINL is reduced by increasing CFIXIncreased phase noiseIncreased power consumptionINL is reduced by controlling RUNo phase noise increaseNo power consumption increase10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a
39、ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits C
40、onference2020 of of 4747RCVS-DTC Circuit Implementation(1 of 2)The implemented RCVS-DTC is composed by 128 switchable cells to control the propagation delay.A voltage-mode DAC controls the value of the cell resistance RU.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a Revers
41、eN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Confere
42、nce2121 of of 4747RCVS-DTC Circuit Implementation(2 of 2)The resistance RUof the unit capacitor cell is implemented by the channel resistance of M3,whose gate voltage is controlled by a 6-bit string resistive DAC.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digit
43、al PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference2222
44、of of 4747RCVS-DTC Circuit Implementation:Simulated INLThe simulated INL shows different profiles based on the DAC voltage VDAC.At high VDACthe T2,INLdominates,while at low VDACthe T1,INLdominates instead.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL w
45、ith a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference2323 of of 47
46、47RCVS-DTC Circuit Implementation:Simulated Phase NoiseThe noise introduced by the DAC has negligible impact on the phase noise of the RCVS-DTC thus its power consumption can be largely reduced.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Rever
47、se-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference2424 of of 4747 DTC-Base
48、d Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Reverse-Concavity Variable-Slope DTC-Adaptive Concavity Zeroing algorithm Implementation and Measurements Conclusions Outline10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reve
49、rse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference2525 of of 4747The DTCI
50、NLreaches a minimum when the two INL sources cancels each other out,leading to a DTCINLwith negligible concavity.This condition is achieved with an adaptive digital algorithm.Adaptive Concavity Zeroing(ACZ)algorithm(1 of 5)10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a Reve
51、rseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Confe
52、rence2626 of of 4747Adaptive Concavity Zeroing(ACZ)algorithm(2 of 5)Different DTCINLconcavity directions cause different profiles of the time error tk.The error signal ek resembles(QEk)2with a sign based on the DTCINL concavity.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a
53、 ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits
54、Conference2727 of of 4747Adaptive Concavity Zeroing(ACZ)algorithm(3 of 5)The sign of DTCINLconcavity can be detected by correlating ek with(QEk)2.To compute(QEk)2a digital multiplier would be required,increasing power consumption.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with
55、 a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuit
56、s Conference2828 of of 4747Adaptive Concavity Zeroing(ACZ)algorithm(4 of 5)Sharing the same concavity sign with(QEk)2,|QEk|can be used,saving power and area consumption.The result hk is used to control VDACvalue,creating a negative feedback loop.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N
57、Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits Confere
58、nceState Circuits Conference2929 of of 4747Adaptive Concavity Zeroing(ACZ)algorithm(5 of 5)The ACZ loop converges when the correlation between ek and|QEk|is nullified,ensuring optimal VDACto achieve minimum RCVS-DTC INL value.10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a R
59、everseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Co
60、nference3030 of of 4747 DTC-Based Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Reverse-Concavity Variable-Slope DTC-Adaptive Concavity Zeroing algorithm Implementation and Measurements Conclusions Outline10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a
61、ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits C
62、onference3131 of of 4747Implemented BBPLL w/RCVS-DTC&ACZ10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitte
63、r and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference3232 of of 4747Simulated algorithms convergence10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concav
64、ity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference3333 of of 4747Die Micrograph and
65、 Power BreakdownProcess:28nm CMOSArea:0.21 mm2Ref.clock:250 MHz10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrate
66、d Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference3434 of of 4747Measured RCVS-DTC Integral Nonlinearity(1 of 3)Measured using phase-modulation method Palattella et al.TCAS1510.110.1:An An 8.758.75GHz Frac
67、tionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid
68、-State Circuits ConferenceState Circuits Conference3535 of of 4747Measured RCVS-DTC Integral Nonlinearity(2 of 3)Measured using phase-modulation method Palattella et al.TCAS1510.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity Variab
69、leConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference3636 of of 4747Measured RCVS-DTC Integral N
70、onlinearity(3 of 3)Measured using phase-modulation method Palattella et al.TCAS1510.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter a
71、nd fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference3737 of of 4747Measured RCVS-DTC Integral Nonlinearity with ACZ calibration Measured using phase-modulation method Palattella et al.TCAS1
72、510.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE Intern
73、ational SolidInternational Solid-State Circuits ConferenceState Circuits Conference3838 of of 4747Measured Fractional Spurs:ACZ OFF10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Ach
74、ieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference3939 of of 4747Measured Fractional Spurs:ACZ ON10.110.1:An An 8.758.75GHz FractionalGHz
75、 Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Ci
76、rcuits ConferenceState Circuits Conference4040 of of 4747Measured Fractional Spurs:Fractional-N Channel Sweep10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.35
77、7.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference4141 of of 4747Measured Fractional-N Phase Noise:ACZ off10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N
78、 Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits Confer
79、enceState Circuits Conference4242 of of 4747Measured Fractional-N Phase Noise:ACZ on10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitte
80、r and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference4343 of of 4747Measured Phase Noise:Fractional-N Channel Sweep10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a
81、 ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits
82、Conference4444 of of 4747Comparison with Prior Art Low-Jitter Fractional-N PLLs(1 of 2)10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Ji
83、tter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference4545 of of 4747Comparison with Prior Art Low-Jitter Fractional-N PLLs(2 of 2)10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N
84、Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits Confere
85、nceState Circuits Conference4646 of of 4747 DTC-Based Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Reverse-Concavity Variable-Slope DTC-Adaptive Concavity Zeroing algorithm Implementation and Measurements Conclusions Outline10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N
86、 Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits Confer
87、enceState Circuits Conference4747 of of 4747Conclusions An 8.75-10.25GHz Fractional-N Bang-Bang PLL achieving57.3fsRMS Jitter and-252.4 dB FoM,exploiting:-Areverse-concavity variable-slope DTC achieving high linearity with low phase noise-An adaptive concavity zeroing algorithm to optimize the RCVS-
88、DTC operating pointAchieves the lowest integrated jitter and highest FoM among low-jitter fractional-N PLLs at near-integer channel10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Ach
89、ieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference4848 of of 4747Please Scan to Rate This Paper10.2:A 5.5s-Calibration-Time,Low-Jitter,an
90、d Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference1 of 4410.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)AlgorithmSeheon Jang*1,2,Munjae
91、Chae*1,2,Hangi Park*1,2,Chanwoong Hwang1,2,and Jaehyouk Choi2(*Equally-Credited Authors)1KAIST,Daejeon,Korea2Seoul National University,Seoul,Korea10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International S
92、olid-State Circuits Conference2 of 44Outline Motivation Strategy for low-jitter and small-area fractional-N DPLL Problem of conv.least mean squares(LMS)multi-variable calibration(MVC)Proposed Frac.-N DPLL Using DCD-RLS MVC and 5-Track M Simplified overall architecture with in-band-noise reduction te
93、chniques Dichotomous coordinate descent-based(DCD)-RLS MVC 5-Track M Overall architecture Measurements and Performance Comparison Conclusions10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-
94、State Circuits Conference3 of 44Outline Motivation Strategy for low-jitter and small-area fractional-N DPLL Problem of conv.least mean squares(LMS)multi-variable calibration(MVC)Proposed Frac.-N DPLL Using DCD-RLS MVC and 5-Track M Simplified overall architecture with in-band-noise reduction techniq
95、ues Dichotomous coordinate descent-based(DCD)-RLS MVC 5-Track M Overall architecture Measurements and Performance Comparison Conclusions10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State
96、 Circuits Conference4 of 44DTCSOUTMMDTDCDTDC SREFDLFDDCWDFCWMCompact LC VCOSDIVStrategy for Low-Jitter and Small-Area Frac.-N DPLLPhase NoisefBWLC VCO NoiseM Q-NoiseOverall Noisefreduced Compact silicon area DPLL w/compact multi-turn LC VCO Natural suppression of VCOs PN Wide loop bandwidth Cancella
97、tion of Q-noise of M Digital-to-time converter(DTC)10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference5 of 44SOUTMMDTDCDTDC SREFDLFDDCWDFCWMCompact LC VCOSDIVDTCDTC wi
98、th thermal noise nonlinearityPhase NoisefBWLC VCO NoiseM Q-NoiseOverall Noisefreduced Noise from DTC:thermal noise remained Q-noise due to nonlinearity Delicate multiple jitter-reduction techniques are requiredStrategy for Low-Jitter and Small-Area Frac.-N DPLL10.2:A 5.5s-Calibration-Time,Low-Jitter
99、,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference6 of 44DTCSDIVSOUTMMDTDCDTDCDMMDSREFDLFDFCWCompact LC VCOMDPSDDCWPSEL 10DQDQW.Wu,ISSCC21 C.Hwang,ISSCC22 1 cal.var.for phase offset cal.DPS10 DQDQDPSSOUTSM
100、MDSDIV 10 DQDQDPSSOUTSMMDSDIV Jitter Reduction Tech.:DTC-Range Reduction10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference7 of 44DTCSDIVSOUTMMDTDCDTDCDMMDSREFDLFDFCWC
101、ompact LC VCOMDPSDDCWPSELDTC NL Cal.DDCW,CALH.Park,ISSCC21DDCW01D DCW,CAL01TDTCTDTCRemained M Q-noise DDCWDTDC DDCW,CAL xn(1)xn(2)xn(3)(en)ACC1()1()2()3ACCACC 23 Jitter Reduction Tech.:DTC NL Calibration 3 cal.vars.for 3rd-order curve fitting DDCW,DDCW2,DDCW310.2:A 5.5s-Calibration-Time,Low-Jitter,a
102、nd Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference8 of 44SOUTMMDDMMDDLFDFCWCompact LC VCOM1 var.DDCW,CALDPSDDCWDTCTDCDTDC3 vars.SDIVSREFMulti-variableCalibrationPSELApproach for Low-Jitter and Small-Area Fra
103、c.-N DPLL 4 input calibration variables DPS,DDCW,DDCW2,DDCW3 Error code DTDC Calibrated code DDCW,CAL10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference9 of 44 ACCn(k)
104、hn(k)hn(4)xn(4)(4)ACCn(k)hn(k)ACCn(k)hn(k)ACCn(1)hn(1)hn(1)enxn(1)(1)xn(k):cal.variables(DPS,DDCW,DDCW2,DDCW3)hn(k):cal.coefficients DDCW,CAL=xn(k)hn(k)DDCWDTDC DDCW,CALxn(1)xn(2)xn(3)enACC DPS xn(4)(1)ACC(2)ACC(3)ACC(4)hn(4)hn(3)hn(2)()1()2()3()1hn(1)Problem of Conventional LMS Multi-Var.Cal.(MVC)L
105、arge calibration step(k)fast cal.(1)(2)(3)(4)to avoid racing Calibration loop with(4):cal.time Least-Mean-Squares(LMS)Multi-Variable Calibration(MVC)10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE Internationa
106、l Solid-State Circuits Conference10 of 44 ACCn(k)hn(k)hn(4)xn(4)(4)ACCn(k)hn(k)ACCn(k)hn(k)ACCn(1)hn(1)hn(1)enxn(1)(1)LMS MVC()1hnxnhnnenRn()TACCRn1 z1 Recursive-Least-Squares(RLS)MVC Comparison between LMS MVC and RLS MVC 4 Calibration variables:xn(k)s xn(1),xn(2),xn(3),xn(4)4 Calibration steps:(k)
107、s(1),(2),(3),(4)4 Calibration coefficients:hn(k)s hn(1),hn(2),hn(3),hn(4)4x1 Cal.vars.vector:xn xn=xn(1)xn(2)xn(3)xn(4)T 4x4 Correlation matrix:Rn Rn=Nn(xnxnT)4x1 Cal.coeff.vector:hn hn=hn(1)hn(2)hn(3)hn(4)T10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Re
108、cursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference11 of 44n(1)(4)n(1)(3)n(1)(2)n(1)(1)hn(1)ACCn(k)hn(k)hn(4)ACCn(k)hn(k)ACCn(k)hn(k)ACChn(1)(4)(1)xn(4)n(1)enxn(1)hn(1)LMS MVC hnRn()TACCz1 RLS MVC 1()1hnnxnenRnSolving normal equation(Rnhn=n)Multiplying fixed s
109、tep(k)s individually Not account for correlation btw xn(k)sComparison between LMS MVC and RLS MVC Solving Normal Eq.Rnhn=n Account for correlation btw xn(k)shnnRn1xn(1)xn(1)xn(1)xn(2)xn(1)xn(4)xn(2)xn(1)xn(2)xn(2)xn(2)xn(4)xn(4)xn(1)xn(4)xn(2)xn(4)xn(4)1=Nnn=1N 10.2:A 5.5s-Calibration-Time,Low-Jitte
110、r,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference12 of 44()1hnxnhnnenRn()TACCRn1 z1 RLS MVC 050hn(k)s10.950.90.8500.050.80.1Time(s)100 150 200 250 300 350 400 450 500hn(1)hn(4)hn(3)hn(2)050hn(k)s10.950.9
111、0.8500.050.80.1Time(s)5hn(1)hn(4)hn(3)hn(2)Comparison between LMS MVC and RLS MVCSimulated calibration transients ACCn(k)hn(k)hn(4)xn(4)(4)ACCn(k)hn(k)ACCn(k)hn(k)ACCn(1)hn(1)hn(1)enxn(1)(1)LMS MVC10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Le
112、ast-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference13 of 44Simulated calibration transientsComparison between LMS MVC and RLS MVCRLS MVC:Fast convergence but High hardware complexity to solve normal equationhnRn()TACCz1 RLS MVC 1()1hnnxnenRn10.2:A 5.5s-Calibration-Time,
113、Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference14 of 44Simulated calibration transientsComparison between LMS MVC and RLS MVCRLS MVC:Fast convergence but High hardware complexity to solve norm
114、al equation Solution:Dichotomous Coordinate Descent-based(DCD)-RLSY.Zakharov,IEEE TSP08hnRn()TACCz1 RLS MVC 1()1hnnxnenRn10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Confe
115、rence15 of 44Outline Motivation Strategy for low-jitter and small-area fractional-N DPLL Problem of conv.least mean squares(LMS)multi-variable calibration(MVC)Proposed Frac.-N DPLL Using DCD-RLS MVC and 5-Track M Simplified overall architecture with in-band-noise reduction techniques Dichotomous coo
116、rdinate descent-based(DCD)-RLS MVC 5-Track M Overall architecture Measurements and Performance Comparison Conclusions10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conferenc
117、e16 of 44Simplified Overall Architecture Dichotomous Coordinate Descent-based(DCD)-RLS MVCTo achieve fast calibration implementing RLS with minimal area and power 5-Track MTo maintain fast calibration at near-integer channelsDTCSDIVSOUTMMDTDCDTDCDMMDSREFCompact LC VCODLFPSELDDCWDPSDFCW5-Track M Meth
118、ods for fast calibrationDCD-RLS MVCDDCW,CAL10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference17 of 44DDCWDPSnxnDDCW,CALn-vector generator(HVG)xnenXVGPCGDDCW(4)DPS(DDC
119、W(4)DPS)2(DDCW(4)DPS)3DPS3i=1xn(i)n(i)DCD-RLS MVCDCD-RLS MVC xn-vector generator(XVG)Converts DDCWand DPSinto 4x1 xn-vector n-vector generator(HVG)Generates n-vector using DCD-RLS algorithm Y.Zakharov,IEEE TSP08 Predistortion-code generator(PCG)Generates predistortion-code using 4x1 vector xnand 4x1
120、 vector n10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference18 of 44DDCWDPSnxnDDCW,CALXVGPCGxnenn-vector generator(HVG)Implementation of DCD-RLS DCD-RLS MVCDCD-RLS MVC
121、 xn-vector generator(XVG)Converts DDCWand DPSinto 4x1 xn-vector n-vector generator(HVG)Generates n-vector using DCD-RLS algorithm Y.Zakharov,IEEE TSP08 Predistortion-code generator(PCG)Generates predistortion-code using 4x1 vector xnand 4x1 vector n10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact
122、-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference19 of 44DDCWDPSDDCW,CALRLSXVGPCGDDCWDPSDDCW,CALXVGPCGDCD-RLS(HVG)DCD-RLS MVCRLS MVChnxnxnenxnennxnMatrixInversionnRnz1 hnACC()TxnxnTACCDCD AlgorithmnRnrnz1 n()Tnz1 xnx
123、nTNormal eq.(Rn hn=n)Iterative processDCD-RLS MVC RLS:Solving normal equation using matrix inversion to find hn DCD-RLS(HVG):Iterative process using DCD algorithm to find approximate hn(n)10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squar
124、es(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference20 of 44 Based on auxiliary normal equation Rnn+rn=n n:approximate hn rn:residual vector n:modified nreflecting rn1 Principle of DCD algorithm rn=n Rnn To minimize rn,find optimal nremoving nusing only Additions and Bit ShiftsIt
125、erative Process using DCD AlgorithmDCD AlgorithmnRnrnnnIterative processz1 1)Find index p(1 p 4)&Set for k=1:16 if Rn(p,p)/2k+1|n(p)|=2k and break else =0DCD Algorithm p=index of the largest element of|n|2)Update n(i)=3)Update rn=n Rnnsign(n(p)(if i=p)(otherwise)010.2:A 5.5s-Calibration-Time,Low-Jit
126、ter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference21 of 441)Find index p(1 p 4)&Set for k=1:16 if Rn(p,p)/2k+1|n(p)|=2k and break else =0DCD Algorithm p=index of the largest element of|n|2)Update n(i)=3
127、)Update rn=n Rnnsign(n(p)(if i=p)(otherwise)0Iterative Process using DCD Algorithm Objective of DCD algorithm To minimize rn=n Rnn 3-step to find n1)Find index p Find optimal step size as =2k Additions and Bit Shifts2)Update nusing p and Bit Shifts3)Update rnbased onauxiliary normal equation Additio
128、ns and Bit ShiftsIteration fREF10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference22 of 44DCD Algorithm2)Update n(i)=3)Update rn=n Rnnsign(n(p)(if i=p)(otherwise)01)Fi
129、nd index p(1 p 4)&Set p=index of the largest element of|n|for k=1:16 if Rn(p,p)/2k+1|n(p)|=2k and break else =0Iterative Process using DCD Algorithm Objective of DCD algorithm To minimize rn=n Rnn 3-step to find n1)Find index p Find optimal step size as =2k Additions and Bit Shifts2)Update nusing p
130、and Bit Shifts3)Update rnbased onauxiliary normal equation Additions and Bit ShiftsIteration fREF10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference23 of 44DCD Algorit
131、hm3)Update rn=n Rnn1)Find index p(1 p 4)&Set p=index of the largest element of|n|for k=1:16 if Rn(p,p)/2k+1|n(p)|=2k and break else =02)Update n(i)=sign(n(p)(if i=p)(otherwise)0Iterative Process using DCD Algorithm Objective of DCD algorithm To minimize rn=n Rnn 3-step to find n1)Find index p Find o
132、ptimal step size as =2k Additions and Bit Shifts2)Update nusing p and Bit Shifts3)Update rnbased onauxiliary normal equation Additions and Bit ShiftsIteration fREF10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEE
133、E International Solid-State Circuits Conference24 of 44DCD Algorithm1)Find index p(1 p 4)&Set p=index of the largest element of|n|for k=1:16 if Rn(p,p)/2k+1|n(p)|=2k and break else =02)Update n(i)=sign(n(p)(if i=p)(otherwise)03)Update rn=n RnnIterative Process using DCD Algorithm Objective of DCD al
134、gorithm To minimize rn=n Rnn 3-step to find n1)Find index p Find optimal step size as =2k Additions and Bit Shifts2)Update nusing p and Bit Shifts3)Update rnbased onauxiliary normal equation Additions and Bit ShiftsIteration fREF10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N D
135、igital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference25 of 44Comparison between MVCs High complexity(100%)w/MULTs and DIVs Fast calibration Moderate complexity(34.4%)w/only ADDs and Bit Shifts Fast calibration Low complexity(16.9%)Slow cali
136、brationenz1()TxnxnxnT rnIterative processnRnnnnDCD Algorithm DCD-RLSz1 ACCenxnnhnhnACCfixed LMSenz1()TxnxnxnT nRnhnhn()1Normal eq.(Rn hn=n)Rn1MatrixInversion RLSACC10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IE
137、EE International Solid-State Circuits Conference26 of 44DTCSDIVSOUTMMDTDCDTDCDMMDSREFCompact LC VCODLFPSELDDCWDPSDFCW5-Track M Methods for fast calibrationDCD-RLS MVCDDCW,CALSimplified Overall Architecture Dichotomous Coordinate Descent-based(DCD)-RLS MVCTo achieve fast calibration implementing RLS
138、with minimal area and power 5-Track MTo maintain fast calibration at near-integer channels10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference27 of 44Pdf t00.90.1Time(T
139、REF/DFRAC)1t0DDCWMASH1-1MDFCWACC DMMDDDCW0Problem of Conventional M Time-variant non-uniform pdf for each track gives limited data to MVC 1 effectively available track providing limited DDCW10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squ
140、ares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference28 of 44Time(TREF/DFRAC)1DDCWt0Pdf t00.20.20.20.20.21st orderMDFCWRNGACC Uniform random integer(1 to 3)1z1DMMDDDCW0Solution:5-Track M Time-invariant uniform pdf for each track gives enough data to MVC 5 constantly available tr
141、acks providing various DDCW10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference29 of 445-Track M w/DTC-Range Reduction To accommodate DTC-range reduction by generating
142、DPS1st orderM2DFCWRNGACC Uniform random integer(1 to 3)1z1DMMDDDCWQz1 DFCW21/2Q DPS W.Wu,ISSCC2110.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference30 of 44DTCSDIVDTCSO
143、UTMMDBBPDTDCMain pathDBBPDDDCWDPSDFCWDTDC,C,M,FDMMDDDCW,CALSREFAux.path5-Track MDTDC,FKI,FKI,MKI,CACCDTDC,C,M,FACCACCACCKP,CDCD-RLS MVCAux.path01Phase Selector(PSEL)DQDQKP,BBKI,BBType-II GSLC VCOOverall Architecture10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsin
144、g the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference31 of 44Overall ArchitectureDTCSDIVDTCSOUTMMDBBPDTDCMain pathDBBPDDDCWDPSDFCWDTDC,C,M,FDMMDDDCW,CALSREFAux.path5-Track MDTDC,FKI,FKI,MKI,CACCDTDC,C,M,FACCACCACCKP,CDCD-RLS MVCAux.path01Phase Selector(P
145、SEL)DQDQKP,BBKI,BBType-II GSCompact LC VCO Small Area High Phase Noise Wide PLL Bandwidth180m 180m 55m x 60m10.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference32 of 44
146、DDCW,CALDTCDTCDCD-RLS MVCDDCWDPS01Phase Selector(PSEL)DQDQLC VCOSDIVSOUTMMDBBPDMain pathDBBPDDFCWDMMDSREF5-Track MDTDC,FACCKP,BBKI,BBType-II GSTDCDTDC,C,M,FAux.pathKI,FKI,MKI,CDTDC,C,M,FACCACCACCKP,CAux.path Auxiliary path using 3 TDCs with different thresholds Fast frequency acquisitionOverall Arch
147、itectureL.Bertulessi,ISSCC1810.2:A 5.5s-Calibration-Time,Low-Jitter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference33 of 44DTCSDIVDTCSOUTMMDBBPDTDCMain pathDBBPDDDCWDPSDFCWDTDC,C,M,FDMMDDDCW,CALSREFAux.p
148、ath5-Track MDTDC,FLC VCOKI,FKI,MKI,CACCDTDC,C,M,FACCACCACCKP,CDCD-RLS MVCAux.path01Phase Selector(PSEL)DQDQKP,BBKI,BBType-II GSType-II Gear ShiftingWhen DBBPD avg.50 x faster than LMS MVC Calibration time:when RMS jitter due to NL 5%of total RMS Jitter LMS MVC:273s10.2:A 5.5s-Calibration-Time,Low-Ji
149、tter,and Compact-Area Fractional-N Digital PLLUsing the Recursive-Least-Squares(RLS)Algorithm 2024 IEEE International Solid-State Circuits Conference39 of 4401002003000hn(4)hn(3)hn(2)hn(1)Time(s)6.51002003000Time(s)0.010.020.010.020.0100.010.0100.010.02110110.776.5RMS jitter due toNL of DTC&PSEL1012
150、101310140.785%of output jitterDCD-RLS MVCCal.time:6.5 sDCD-RLS MVCMeasured Calibration Transients Measured calibration time at DFRAC=213 DCD-RLS MVC:6.5s DCD-RLS MVC w/5-Track M:fast calibration at a near-integer channel Calibration time:when RMS jitter due to NL 20dB reduction Conv.PLLThis workspur
151、 frequency shifted to 12.5MHzPLL Jitter ComparisonConv.DTC-based Frac-N PLL712 fsDither-PLL129 fsThis Work119 fsInt-N PLL89fs10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International So
152、lid-State Circuits Conference16 of 39Outline IntroductionBackground and MotivationPrior Arts of Fractional-Spur Suppression Technique Proposed Low-Spur Fractional-N PLLCascaded Fractional DividerPseudo-differential DTC Measurement Results and Comparison Conclusions10.3:A 7GHz Digital PLL with Cascad
153、ed Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference17 of 39Noise-Linearity Trade-Off in DTCs(1/2)Variable-Slope DTC:Slope-dependent nonlinearity is generated at comparator Potentiall
154、y low delay offset,good for phase noiseRDACIbiasVinVxVDDVoutCVxVinVouttimetofstdelay rangeVthVminVmaxVxVinVouttimetofstdelay rangeVthVDDVinVoutVxRC10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024
155、 IEEE International Solid-State Circuits Conference18 of 39Noise-Linearity Trade-Off in DTCs(2/2)Constant-Slope DTC:No slope-dependent nonlinearity source Vmaxmust be kept low to avoid nonlinearity from Ibias Long delay offset,moderate phase noise performanceRDACIbiasVinVxVDDVoutCVxVinVouttimetofstd
156、elay rangeVthVminVmaxVxVinVouttimetofstdelay rangeVthVDDVinVoutVxRCJ.Ru,JSSC,1510.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference19 of 39Pseudo-Di
157、fferential DTC(1/6)DTC delay increases with increasing QN in conventional design.TdcoDctrlN-1NDiv.Ratiokqnk0Tdcok dtckk0TdcoDTCrefPDpdMMDfbdcoDctrl dtc+inlDTC INL inlDctrlDmax-Dmax0a1(1-4()2)Dctrl2DmaxDctrl2Dmax+a2()2-)Dctrl2Dmax14(Dctrl)=inlodd symmetriceven10.3:A 7GHz Digital PLL with Cascaded Fra
158、ctional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference20 of 39Pseudo-Differential DTC(2/6)Both odd/even-symmetric INL components appear at PD output.TdcoDctrlN-1NDiv.Ratiokqnk0Tdcok dtckk0Tdc
159、oDTCrefPDpdMMDfbdcoDctrl dtc+inlDTC INL inlDctrlDmax-Dmax0a1(1-4()2)Dctrl2DmaxDctrl2Dmax+a2()2-)Dctrl2Dmax14(Dctrl)=inlodd symmetriceven10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE Inter
160、national Solid-State Circuits Conference21 of 39Pseudo-Differential DTC(3/6)Relative delay can be implemented by two half-ranged DTCs0.5TdcoDctrl0.5TdcoDctrlDTCprefPDpdMMDfbdcoDctrl dtcn+inln dtcp+inlpDTCnDTC INLDctrlDmax-Dmax0 inlp inlnb1(1-4()2)Dctrl2DmaxDctrl2Dmax+b2()2-)Dctrl2Dmax14 inlp(Dctrl)=
161、-b1(1-4()2)Dctrl2DmaxDctrl2Dmax+b2()2-)Dctrl2Dmax14 inln(Dctrl)=odd-symmetriceven-symmetricqnk0Tdcok dtcpkk00.5Tdco10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State
162、Circuits Conference22 of 39Pseudo-Differential DTC(4/6)The delay of DTCndecreases with increasing QN0.5TdcoDctrl0.5TdcoDctrl dtcnkk00.5Tdcoqnk0Tdcok dtcpkk00.5TdcoDTCprefPDpdMMDfbdcoDctrl dtcn+inln dtcp+inlpDTCnDTC INLDctrlDmax-Dmax0 inlp inlnb1(1-4()2)Dctrl2DmaxDctrl2Dmax+b2()2-)Dctrl2Dmax14 inlp(D
163、ctrl)=-b1(1-4()2)Dctrl2DmaxDctrl2Dmax+b2()2-)Dctrl2Dmax14 inln(Dctrl)=odd-symmetriceven-symmetric10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conferenc
164、e23 of 39Pseudo-Differential DTC(5/6)INL can be suppressed because of the reduced delay range Even-symmetric INL components are identical for the two DTCs0.5TdcoDctrl0.5TdcoDctrl dtcnkk00.5Tdcoqnk0Tdcok dtcpkk00.5TdcoDTCprefPDpdMMDfbdcoDctrl dtcn+inln dtcp+inlpDTCnDTC INLDctrlDmax-Dmax0 inlp inlnb1(
165、1-4()2)Dctrl2DmaxDctrl2Dmax+b2()2-)Dctrl2Dmax14 inlp(Dctrl)=-b1(1-4()2)Dctrl2DmaxDctrl2Dmax+b2()2-)Dctrl2Dmax14 inln(Dctrl)=odd-symmetriceven-symmetric10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter
166、2024 IEEE International Solid-State Circuits Conference24 of 39Pseudo-Differential DTC(6/6)Even-symmetric INL cancels each other because of the time-domaindifferential operation of PD,noise-linearity trade-off is much relaxed0.5TdcoDctrl0.5TdcoDctrl dtcnkk00.5Tdcoqnk0Tdcok dtcpkk00.5TdcoDTCprefPDpdM
167、MDfbdcoDctrl dtcn+inln dtcp+inlpDTCn inldiff(Dctrl)=inlp(Dctrl)-inln(Dctrl)=2b1(1-4()2)Dctrl2DmaxDctrl2Dmaxonly odd-symmetric componentsDTC INL inlp inln inldiffDctrlDmax-Dmax010.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 1
168、43.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference25 of 39Outline IntroductionBackground and MotivationPrior Arts of Fractional-Spur Suppression Technique Proposed Low-Spur Fractional-N PLLCascaded Fractional DividerPseudo-differential DTC Measurement Results and Compar
169、ison Conclusions10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference26 of 39Circuit Implementation(1/3)fbqnfineLSBsMMDdcoBBPDrefqnmainMASH1MASH1-1-+
170、-+fcwauxDTCmainqnauxfcwmainfcwintDSMmainDSMauxKdtcfineDTCauxDTCfineKdtcauxKdtcmainbpdCascaded Divider10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Confe
171、rence27 of 39Circuit Implementation(2/3)fbqnfineLSBsMMDdcoBBPDrefqnmainMASH1MASH1-1-+-+fcwauxDTCmainqnauxfcwmainfcwintDSMmainDSMauxKdtcfineDTCauxDTCfineKdtcauxKdtcmainbpdPseudo-diff.DTCsCascaded Divider6-bit280ps range3-bit140ps range6-bit4.4ps range10.3:A 7GHz Digital PLL with Cascaded Fractional D
172、ivider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference28 of 39Circuit Implementation(3/3)DTC ControlPseudo-diff.DTCsDTC Range Reduction6-bit280ps range3-bit140ps range6-bit4.4ps rangefbqnfineLSBsMMDCM
173、L/2dcoBBPDrefqnmain1/2MASH12MASH1-1-+-+2sumpselcarrycarry1/2sumfcwauxDTCmainqnaux1/2MPGfcwmainMSBsMSBs1/2divfcwintDSMmainDSMauxKdtcfineDTCauxDTCfineKdtcauxKdtcmainbpdMulti-Phase Generator(MPG)012muxfdcofdivpselffbMulti-Phase Generator(MPG)bpd qnauxqnmainqnfineKdtcauxKdtcmainKdtcfineDTC Gain Calibrat
174、ion10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference29 of 39Die Micrograph1320 um1100 umDCO/2MMDDTCauxPDSPIDigitalBUFDTCmainDTCfinePower Breakdow
175、nBlockPower(mW)DTC_C0.67DTC_F0.5DTC_AUX0.58Digital0.34DCO3.3Divider+PD+Other3.5Total8.89DTCmainDTCfineDTCaux Process:65nm CMOS Core Area:0.23mm2 Reference:100MHz Power:8.89mW10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143
176、.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference30 of 39Measured DTC INL00.511.52Measured Single DTC INLINL psDctrl-15-10-5051015DTC Delay Range:280psDTCpDTCnDTCdiffDifferential Delay Range:280psDctrl-0.4-0.20.00.20.40.60.81.01.2INL psMeasured Pseudo-Diff.DTC INL-15-10-
177、5051015 Peak-to-peak INL reduced from 0.79%to 0.21%with pseudo-differential architecture*INL is measured by the method in C.Palattela,TCAS-II,1510.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IE
178、EE International Solid-State Circuits Conference31 of 39Measured Phase NoiseCascaded Divider Technique OffIntegrated Jitter:243.5 fsCascaded Divider Technique OnIntegrated Jitter:143.7 fs Integrated jitter reduced from 243.5fs to 143.7fsMeasured at near-integer channel nearby 7GHz10.3:A 7GHz Digital
179、 PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference32 of 39Measured Fractional Spur Level-45.4dBc98kHz-62.1 dBc195kHz Fractional spur was suppressed from-45.4dBc to-6
180、2.1dBcMeasured at near-integer channel nearby 7GHzCascaded Divider Technique OffCascaded Divider Technique On10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circui
181、ts Conference33 of 39Measured Fractional Spur LevelMeasured at near-integer channels nearby 7GHz2-152-142-132-122-112-102-92-82-72-6Fractional FCW-70-65-60-55-50-45-40Fractional Spur dBc-75Cascaded Divider Technique OnCascaded Divider Technique Off10.3:A 7GHz Digital PLL with Cascaded Fractional Div
182、ider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference34 of 39Comparison to Prior Arts(1/3)*FoM=10log(Power/1mW)*(Jitter/1s)2)*FoMref=10log(Power/1mW)*(Jitter/1s)2)+10log(fref/10MHz)*Normalized to outpu
183、t frequencyThis WorkG.CastoroISSCC23M.MercandeliISSCC21A.SanticcioliJSSC21S.Dartizio ISSCC23Z.GaoISSCC22J.KimISSCC21W.WuISSCC21Process(nm)6528282828406514TopologyDPLLDPLLDPLLDPLLDPLLDPLLDPLLSPLLTechniqueCascaded Divider+Pseudo-Diff.DTCMulti DTCDTC GainCalibrationReplica DTC+RetimingICS DTC+FCW Dithe
184、rTAU+DPDVDAC+DPDDTCRangeReductionw/i DPD?NoNoNoNoNoYesYesNoFref(MHz)02504015076.8Fpll(GHz)6.57.59.2510.7512.915.112.815.29.2510.52.564.114166.2Frac.Spur(dBc)-62.1-60.3-50.4-61-71.9-59-61-66.4*fref(MHz)fpll(MHz)10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differentia
185、l DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference35 of 39Comparison to Prior Arts(2/3)*FoM=10log(Power/1mW)*(Jitter/1s)2)*FoMref=10log(Power/1mW)*(Jitter/1s)2)+10log(fref/10MHz)*Normalized to output frequencyThis WorkG.Casto
186、roISSCC23M.MercandeliISSCC21A.SanticcioliJSSC21S.Dartizio ISSCC23Z.GaoISSCC22J.KimISSCC21W.WuISSCC21Jitter(fs)143.777.1107.666.276.718210493.2Power(mW)8.8917.910.819.817.23.487.314.2FoM*-247.4-249.7-249.0-250.6-249.9-249.4-251.0-249.1FoM_ref*-237.4-235.8-235.1-233.6-236.0-243.4-239.3-240.2Area0.230.
187、360.160.170.330.310.210.31FoMref*10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference36 of 39Comparison to Prior Arts(3/3)D.YangJSSC22W.WuISSCC21J.K
188、imISSCC21A.SanticcioliISSCC23FoM dB-260-250-240-230-220This WorkFoMref=-250dBFoMref=-230dBFoMref=-220dBReference Frequency MHz0500G.CastoroISSCC23S.DartizioISSCC23D.CherniakRFIC18H.ParkISSCC21Q.ZhangISSCC23C.HoISSCC16D.MurphyJSSC23C.Ho ISSCC18Q.ZhangISSCC21FoMref=-237.4dBPrior-Art PLLs wi
189、th-60dBc Frac.SpurAnalog PLLDigital PLLPLL w/i DPDC.YaoISSCC17D.YangISSCC1910.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference37 of 39Outline Intro
190、ductionBackground and MotivationPrior Arts of Fractional-Spur Suppression Technique Proposed Low-Spur Fractional-N PLLCascaded Fractional DividerPseudo-differential DTC Measurement Results and Comparison Conclusions10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC
191、Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference38 of 39Conclusions A 7GHz fractional-N DPLL achieving-62.1dBc fractional spur and 143.7fs integrated jitter from 100MHz reference utilizing:A cascaded fractional divider to push fr
192、actional spurs to out-of-bandA pseudo-differential DTC with self-canceled even-order INL Fractional spur suppression is achieved with no DPD and no elevated random noise10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs
193、Integrated Jitter 2024 IEEE International Solid-State Circuits Conference39 of 39Acknowledgement This work is partially supported by NICT(JPJ012368C00801),MIC(JPJ000254),JST(JPMJFS2122),STAR,and VDEC incollaboration with Cadence Design Systems,Inc.,MentorGraphics,Inc.,and Keysight Technologies Japan
194、,Ltd.10.3:A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1dBc Fractional Spur and 143.7fs Integrated Jitter 2024 IEEE International Solid-State Circuits Conference40 of 39Please Scan to Rate This Paper10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Inte
195、ger-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference1 of 36 A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering
196、 SpursMichael Peter Kennedy1,2 Valerio Mazzaro1,2Stefano Tulisi3 Michel Scully3Niall McDermott3James Breslin31University College Dublin,Dublin,Ireland2Microelectronic Circuits Centre,Dublin,Ireland3Analog Devices,Limerick,Ireland10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur
197、BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference2 of 36 Outline Motivation Prior Art ENOP Digital Modulator(DM)Demonstrator Architecture Measurement Results Conclusions10.4:A 45.5fs-Integrated-Random-Jitter and-75
198、dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference3 of 36 Motivation Fractional-N CP-PLL Nonlinearity-induced noise and spurs Horn spurs Wandering spurs10.4:A 45.5fs-Integrated-Random-Jitte
199、r and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference4 of 36 Fractional-N PLLDivider controller introduces shaped quantization noise10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Int
200、eger-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference5 of 36 Nonlinear distortion of accumulated quantization noise eacccauses noise and spursNonlinearity-Induced Noise and Spurs10.4:A 45.5fs-Integra
201、ted-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference6 of 36 Fractional-N PLL10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N
202、PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference7 of 36 Horn Spurs and Wandering Spurs Horn spurs:fixed in time,occur in pairs,and dependent on initial conditions Wandering spurs:time-varyingD.Mai ESSCIRC21V.Mazzaro TCASII 2010.4:A 4
203、5.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference8 of 36 Outline Motivation Prior Art ENOP DM Demonstrator Architecture Measurement Results Conclusions
204、10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference9 of 36 Prior Art Successive RequantizerK.Wang ISSCC08 Probability Mass Redistributor M.P.Kenn
205、edy ISSCC19 Time-Invariant Probability Modulator T.Seong ISSCC21 Probability Density Shaping H.Park ISSCC21 Enhanced Nonlinearity-induced noise Performance(ENOP)V.Mazzaro TCASI 2210.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fracti
206、onal,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference10 of 36 Prior Art:Successive RequantizerSuccessive Requantizer immune to cubic distortionK.Wang ISSCC0810.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression
207、 of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference11 of 36 Prior Art:ENOP Sequence eaccn is immune to spurious tones(spurs)up to order h if eaccpn is free of tones for 0 p h The order of immunity is bounded by the spread of the accumulated error eacc If r
208、 eacc r then the maximum order of immunity to spurs is(2r-1):popt=2r-1E.Familier TSP 13,V.Mazzaro TCASI 2210.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuit
209、s Conference12 of 36 Outline Motivation Prior Art ENOP DM Demonstrator Architecture Measurement Results Conclusions10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-Stat
210、e Circuits Conference13 of 36 ENOP DM:Definitions r:the half width of the range of the accumulated quantization error p:the order of polynomial nonlinearities up to which the accumulated quantization error is immune from spurs 2eacc:the variance of the accumulated quantization error p=poptand minimu
211、m 2eacc=r/6V.Mazzaro TCASI 2210.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference14 of 36 ENOP DMNoise Transfer Function is =1 1(1+=11)where the c
212、oefficients ciare chosen such that 1+=11=0r=(1+=11|)/2;popt=2r 1;2eacc,min=r/610.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference15 of 36 ENOP vs
213、 MASH 1-1-1 MASH 1-1-1=1 1 21 1r=2;popt=3;p=2 popt,2eacc=3/6(both suboptimal)ENOP P9=1 1 21 2 4+6+7 9r=5;popt=9;p=9=popt,2eacc=5/6(both optimal)10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024
214、IEEE International Solid-State Circuits Conference16 of 36 Outline Motivation Prior Art ENOP DM Demonstrator Architecture Measurement Results Conclusions10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Sp
215、urs 2024 IEEE International Solid-State Circuits Conference17 of 36 Implementation:PLL Type-II fractional-N frequency synthesizer 0.18m SiGe BiCMOS 6.4 to 12.8GHz VCO Divide-by-1/2/4/8 PFD and charge pump Fourth-order passive loop filter off chip10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integ
216、er-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference18 of 36 Implementation:Programmable Charge Pump Binary weighted bipolar charge pump with bleedOUTBiasGenerator5VConstant Positive BleedConstant Neg
217、ative BleedPump UpPump Down10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference19 of 36 Implementation:Multi-core VCO Four cores covering 6.4 to 1
218、2.8GHz Pseudo-differential Colpitts architecture 8-bit CDAC,varactor and inductance-133dBc/Hz open loop phase noise 1MHz offset from 7GHz10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE In
219、ternational Solid-State Circuits Conference20 of 36 Implementation:Divider Controller Two variants:26-bit dithered MASH and ENOP10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE Internation
220、al Solid-State Circuits Conference21 of 36 Chip MicrographCALIBRATIONBAND SEL.10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference22 of 36 Outline
221、 Motivation Prior Art ENOP DM Demonstrator Architecture Measurement Results Conclusions10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference23 of 3
222、6 Measurement Results Integer Boundary Spurs Phase Noise and Jitter Horn Spurs Wandering Spurs10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference
223、24 of 36 Integer Boundary Spurs IBS spur reduced by 10dB with ENOP vs MASHENOP:IBS spur-79dBcMASH:IBS spur-69dBc10kHz10kHz10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Sol
224、id-State Circuits Conference25 of 36 Integer Boundary SpursIBS spur is below-75dBc-120-115-110-105-100-95-90-85-80-75-70-65-60000100000IBS spur level dBcOffset frequency kHzMASHENOP10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppress
225、ion of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference26 of 36“Worst Case”Fractional Spurs Worst case fractional spur(due to output buffer)is unaffectedMASHENOPIBSIBS reducedWorst spur unchanged10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Bound
226、ary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference27 of 36 Phase Noise and Jitter 6.56GHzMASH 6.56GHzENOP 6.56GHzRMS jitter w/o spurs 42.9fsRMS jitter w/o spurs 45.5fs10.4:A 45.5fs-Integrated-Random-Jitter
227、and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference28 of 36 Phase Noise and Jitter 9.25GHzMASH 9.25GHzENOP 9.25GHzRMS jitter with spurs 36.2fsRMS jitter with spurs 37.6fs10.4:A 45.5fs-
228、Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference29 of 36 Horn SpursMASH exhibits horn spurs;ENOP does notMASH:Horn spurs -88dBcENOP:no horn spurs10.4:A 45.5
229、fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference30 of 36 Wandering Spurs MASH exhibits wandering spurs;ENOP does notMASH:X indicates wandering spursENOP:
230、no wandering spurs10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference31 of 36 Power ConsumptionmAVmWCharge Pump565280VCO 5V1295645VCO 3.3V243.379
231、Level Shift53.317Reference,PFD and Feedback divider1603.3528LDO and Synchronization353.3116Output divider and RF buffers1263.341610.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE Internatio
232、nal Solid-State Circuits Conference32 of 36 Performance Summary&ComparisonReferenceThis workE.Familiar CICC17M.P.Kennedy ISSCC19W.Wu ISSCC21H.Park ISSCC21S.M.DartizioISSCC23PLL ArchitectureCP-PLLCP-PLLCP-PLLSampling PLLADPLLBB-PLLFractional Spur Suppression MethodENOPMASHSRPMRDTC Range ReductionDTC-
233、NC+PDS DMICS DTC+FCW Subtractive DitherTechnology 180m65nm180m14nm65nm28nmSupply(V)3.3/5.01.0/2.01.2/3.3/5.011.21.2/3.3/5.0Power Consumption(mW)210019.5211814.29.2717.2Area(mm2)13.20.34113.20.310.1460.33Frac.Freq.resn.bits 491639101513fvcoGHz6.4 to 12.83.354 to 85 to 75.2 to 69.25 to 10.5frefMHz198.
234、762661.44153.6100250Loop Bandwidth kHz35048100N/AN/AN/A10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference33 of 36 Performance Summary&Comparison
235、*FoMIBS=Largest IBS spur(sweep)normalized to 1 GHz output frequency;*FoMNPNF=PNmin-10log(fref)-20log(N);*FoMS=10 log(Power/1mW).(Jitter/1s)2ReferenceThis workENOP MASHE.Familiar CICC17M.P.Kennedy ISSCC19W.Wu ISSCC21H.Park ISSCC21S.M.DartizioISSCC23Reference Spur dBc-118-121-79-110-72-77-70.5RMS Jitt
236、er w/o spurs fs45.542.9N/AN/A80.0N/A75.9RMS Jitter w/spurs fs46.445.2N/AN/A93.236576.7Integration Bandwidth10k to 100M10k to 100MN/AN/A10k to 40M10k to 30M 10k to 100MLargest IBS spur(sweep)dBc-75 6.56GHz-69 6.56GHz-72 3.35GHz-72 4.485GHz-72.4 6.45GHz-63 5.3GHz-70 9.25GHz*FoMIBSdBc-91-85-82-85-88-77
237、-89Minimum In-band Phase Noise dBc/Hz-117.6 at 30kHz-118.2 at 30kHz-87.5 10kHz-98.4 50kHzN/AN/AN/A*FoMNPNFdB-231.0-231.6-203.9-211.2N/AN/AN/A*FoMSdBN/AN/AN/AN/A-249.1-239.1-249.910.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractio
238、nal,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference34 of 36 Outline Motivation Prior Art ENOP DM Demonstrator Architecture Measurement Results Conclusions10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression o
239、f Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference35 of 36 Conclusions A fractional-N charge pump PLL has been presented with 45.5fs-Integrated-Random-Jitter 6.56GHz Largest worst-case Integer Boundary Spur(sweep)is-75dBc Horn and wandering spurs are also s
240、uppressed10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE International Solid-State Circuits Conference36 of 36 Acknowledgements Science Foundation Ireland Investigator Grant 13/IA/1979 an
241、d 20/FFP-A/8371 Enterprise Ireland Technology Centre Grant T-2015-0019Microelectronic Circuits Centre Ireland(MCCI)Analog Devices10.4:A 45.5fs-Integrated-Random-Jitter and-75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional,Horn,and Wandering Spurs 2024 IEEE Internatio
242、nal Solid-State Circuits Conference37 of 36 Please Scan to Rate This Paper10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference1 of 2910.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur
243、Fractional-N Sampling PLLUsing a Nonlinearity-Replication TechniqueYuhwan Shin1,2*,Junseok Lee1,2*,Juyeop Kim1,2*,Yongwoo Jo1,2,and Jaehyouk Choi21KAIST,Daejeon,Korea2Seoul National University,Seoul,Korea*Equally Credited Authors(ECAs)10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Samp
244、ling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference2 of 29Outline Introduction Problems of conventional fractional-N PLLs using DTC Proposed Fractional-N SPLL Using an NL-Replication Technique SPD NL-Replication(SNL-REP)Complementary voltage com
245、parator(VC)Implementation of Proposed Fractional-N SPLL Measurements and Performance Comparison Conclusions10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference3 of 29tSREFVSPDDVCSPD
246、SDIVDTCSDTCVREFor BBPDACCMDFRACVCMMDDLFVCODTCSOUTDINTDAQLinear DTCfPSDtVREF01t0TVCODAQDTC1TVCODTC-Based Fractional-N PLLs Requiring a dedicated method to cancel M Q-error Common Solution:Adjusting DTC delay to cancel M Q-error10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLU
247、sing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference4 of 29tSREFVSPDDVCSPDSDIVDTCSDTCVREFor BBPDACCMDFRACVCMMDDLFVCODTCSOUTDINTDAQNonlinear DTCfPSDnTREF/DFRACtTREF/DFRACVREF01t0TVCODAQDTC1TVCOProblems of DTC-Based Fractional-N PLLs Periodic fluctuation in
248、duced by inherent nonlinearity of DTC(NLDTC)Fractional spurs and Q-error leakage10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference5 of 29SREFVSPDDVCSPDSDIVDTCSDTCVREFor BBPDACCMDF
249、RACVCMMDDLFVCODTCSOUTDINTDAQNonlinear DTCfPSDnTREF/DFRACtTREF/DFRACVREFDAQDTC=fDTC(DDCW)Digital Pre-DistortionDAQDDCWDPD=fDTC1(DTC)DDCWPrior Solution I:Digital Pre-DistortionS.Levantino et al.,JSSC14 Digital Pre-Distortion to compensate for the NLDTC10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fr
250、actional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference6 of 29SREFVSPDDVCSPDSDIVDTCSDTCVREFor BBPDACCMDFRACVCMMDDLFVCODTCSOUTDINTDAQNonlinear DTCfPSDnTREF/DFRACtTREF/DFRACVREFDAQDTC=fDTC(DDCW)Digital Pre-DistortionDAQDDCWDPD=fDTC1(DTC
251、)DDCW(1)Piecewise Linearization(2)Polynomial CalibrationDAQDDCW01g0g1g2g3g4DAQDDCW01=g0DAQ+g1DAQ2+g2DAQ3DAQ DDCWDVCLMS-based Calibratorg(gain coefficient)Problems of Digital Pre-Distortion Digital Pre-Distortion to compensate for the NLDTC Requires significant design resources for high accuracyS.Lev
252、antino et al.,JSSC14H.Park et al.,ISSCC21&J.Kim et al.,ISSCC2110.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference7 of 29SREFVSPDDVCSPDSDIVDTCSDTCVREFor BBPDACCMDFRACVCMMDDLFVCODTCS
253、OUTDINTDAQDTC w/Superior LinearityfPSDnTREF/DFRACtTREF/DFRACVREFDAQDTCPrior Solution II:Linear DTCsS.M.Dartizio et al.,ISSCC23 Linear DTC naturally having a small NLDTC10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE Intern
254、ational Solid-State Circuits Conference8 of 29SREFVSPDDVCSPDSDIVDTCSDTCVREFor BBPDACCMDFRACVCMMDDLFVCODTCSOUTDINTDAQDTC w/Superior LinearityfPSDnTREF/DFRACtTREF/DFRACVREFDAQDTC(1)Constant-Slope DTC(2)Inverse Constant-Slope DTCt0VthStill,Longpre-charge timeVDTCkTVCOtVDTC0VthLong offset delayVDACDTC r
255、angeVOUTCI VTHVDTCDACVOUTC(K1)IVTHVDTCI PGBetter linearityProblems of Linear DTCs Linear DTC naturally having a small NLDTC Increases thermal noise,and hence the in-band phase-noiseS.M.Dartizio et al.,ISSCC23J.Z.Ru et al.,JSSC1510.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PL
256、LUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference9 of 29DAQQE(SREFSDIV)VSPDVDACDVC(VSPDVDAC)t SREFVDACVSPDSPDDACSDIVACCMDFRACDAQNLSPDLinear DACMMDVCODVCDAC-Based Voltage-Domain Q-error Cancellation Locating DAC to generate VDACand cancel Q-error afte
257、r SPD Linear DAC cannot track the Q-error of VSPD distorted by NLSPD Still requires a complicated calibrator,such as DPD10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference10 of 29D
258、AQQE(SREFSDIV)VSPDVRNL-DACDVC(VSPDVRNL-DAC)t SREFVRNL-DACVSPDSPDRNL-DACSDIVACCMDFRACDAQNLSPDReplicated NLSPDReplica-NLDACSPD NL-Replication(SNL-REP)MMDVCODVCProposed SPLL Using an NL-Replication Technique Proposed SPD NL-Replication(SNL-REP)Using a DAC that intrinsically has the same NL as the SPD(N
259、LSPD)Can track NLSPDw/o complicated calibrator consuming power&area10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference11 of 29NLSPDSREFVRNL-DACVSPDSPDRNL-DACSDIVACCMDFRACDAQReplica
260、ted NLSPDReplica-NLDACSPD NL-Replication(SNL-REP)DVCVSPDQESREFSDIV=TVCODAQCI VRNL-DACTVCOCI DAQSPDRNL-DAC0 dtDAQTVCOVRNL-DAC=CI0 dtVSPD=CIQEVTVCOttVQE=TVCODAQConcept of SPD NL-Replication(SNL-REP)Design the RNL-DAC with the same structure of an SPD SPD:Charging C with a fixed current of I during QE(
261、=TVCODAQ)RNL-DAC:Charging C with a current of IDAQduring TVCO10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference12 of 29VSPDQESREFSDIV=TVCODAQCI VRNL-DACTVCOCI DAQSPDRNL-DAC0 dtDAQ
262、TVCOVRNL-DAC=CI0 dtVSPD=CIQEVTVCOttVQE=TVCODAQSPDRNL-DAC TVCO=dV0VRNL-DACC(V)I(V)TVCO=C(V)I(V)dV0VSPD1DAQ QE=C(V)I(V)dV0VSPD1DAQ TVCO=C(V)I(V)dV0VRNL-DAC1DAQSame profileTVCODAQ=In practice,is a function of V,i.e.,C(V)I(V)CIVSPD=VRNL-DACalways,For any DAQs,Robustness to NL Due to Voltage-Dependence I
263、n practice,voltage-dependence of I and C can distort the profile Basically,two circuit have the same profile of C(V)/I(V)VSPDand VRNL-DACshould always be the same irrespective of DAQ10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 20
264、24 IEEE International Solid-State Circuits Conference13 of 29SREFVRNL-DACVSPDSPDRNL-DACSDIVACCMDFRACDAQVCConventional Voltage Comparator(VC)1DAQVSPD&VRNL-DAC00Out of the Operation Range of VCLimited RangeDynamic Range of PMOSVSPD(DAQ=1)DVCDesign Issue of Voltage Domain Q-error Cancellation Widely va
265、rying input voltages due to Q-error information Limited dynamic range of conventional VC Reducing the gain of SPD Degrading in-band PN10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Confe
266、rence14 of 29SREFVRNL-DACVSPDSPDRNL-DACSDIVACCMDFRACDAQVCComplementaryProposed Complementary VC1DAQ1/2VSPD&VRNL-DAC 0100High VLow VDAQ 10Dynamic Range of PMOSDynamic Range of NMOSVSPD(DAQ=1)DVCProposed Complementary VC NMOS and PMOS-type VCs with dynamic selection scheme Wide dynamic range of comple
267、mentary VC Guarantee the moderate gain of SPD Excellent in-band PN10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference15 of 2912LC-VCOSOUTMMDSREF Digital Logic DFDTCSDIVDAQ10:0MDFRA
268、CDINTACCDVCVSPDSRESAMPDDAC,GSMMDSPD&RNL-DAC for SNL-REPSMMDDAQ10SVCDVCDAQSOUTSMMDFine-DTCDAQ10:6VRNL-DACComplementary VCSPDRNL-DACPIDLFMASH 1-1Resampler10.5Overall Architecture of Digital SPLL Using an NL-Replication Type-ll SPLL consisting of SPD,DAC,VC,DLF,LC-VCO,and MMD Achieving low jitter using
269、 SNL-REP and complementary VC10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference16 of 29QDACCQDACVOUTSPGDSWBDI,GIQDAC31:0 B2TDSWTAvailableto calibrate5%mismat.RNL-DACSPDVSPDVRNL-DA
270、CDAQ10:6 DDAC,GSMMDSPG,DACSOUTD QD QD Q2TVCOQDACSREFSPG,SPDSDIVPulse Generator(PG)0.51QE2TVCODAQ=QDACSPGDSWBDI,GVOUTD QRD QRSPGDSWBDI,GVOUTPulse Generator(PG)Implementations of SPD&RNL-DAC for SNL-REP Pulse generator(PG)and charge-integrating DAC(QDAC)Share same core circuit Same voltage dependence
271、Same NL10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference17 of 29ChargingDecisionDVC=1ERR2TVCODAQ of total SWsare turned onAll SWsare turned onPhase:SVCSREFSPG,SPDSDIVVSPD,VRNL-DA
272、CSPDRNL-DACSPG,DACSMMDSOUTRNL-DACSPDVSPDVRNL-DACDAQ10:6 DDAC,GSPG,DAC2TVCOSPG,SPD0.51QE2TVCODAQ=QDACSREFSDIVSMMDSOUTPGQDACPGTiming Diagram of SPD&RNL-DAC for SNL-REP After the charging phase,the VC samples VSPDand VRNL-DAC DVCcan be determined purely by the phase error in output signal10.5:A 76fsrms
273、-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference18 of 2960RMS INL(V)0Number of samples50080 100 120460 480 500 520250MC Simulation Results INLSPD03115723DAQ10:6INL(mV)0.80.02.4INLS
274、PDINLRNL-DAC1.6Peak INL=1.71mVRMS INL=498V (3 value)520VSimulated INL of SNL-REP Considerably high RMS INL,despite various layout efforts10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Co
275、nference19 of 2960RMS INL(V)0Number of samples50080 100 120460 480 500 520250MC Simulation Results INLSPDINLRNL-DACINLSPD03115723DAQ10:60.80.02.4INL(mV)1.6031157230.10.0INLSPDINLRNL-DAC0.2Peak INL=253VRMS INL=80V0.3INL(mV)0.80.02.4INLSPDINLRNL-DAC1.6Peak INL=1.71mVRMS INL=498VSNL-REP (3 v
276、alue)520V100V Simulated INL of SNL-REP Cancellation of two NL profiles each other Significant improvement of INL due to SNL-REP10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference20
277、 of 29SREFVRNL-DACVSPDDVCSPDRNL-DACSDIVACCMDFRACDAQ10:6MMDVCOFine-DTCDAQ5:0Coarse ResolutionIN OUTDAQ5:0Fine-DTC(VS-DTC)Q-noise Cancellation with Fine-DTC 6b Fine-DTC to further reduce Q-error Negligible thermal noise and INL due to the narrow dynamic range10.5:A 76fsrms-Jitter and 65dBc-Fractional-
278、Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference21 of 29Digital Logic(Integrated Calibrator)DAQ10:6F DFDTCC DDAC,GDVCDAQ5:01DAQ5:0Delay of Fine-DTC00DFDTC2TVCO/321DFDTC1DAQ10:600DDAC,GVSPD 2TVCO1DDAC,GSampled Voltage of
279、RNL-DACInitial range of Fine-DTC Target(2TVCO/32)Initial range of RNL-DAC Target(VSPD 2TVCO)Integrated Calibrator:RNL-DAC and Fine-DTC Simple gain calibrations to fit in the desirable range Only two coefficients Requires few design resources10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-
280、N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference22 of 29NMOS VCDouble-tail Comparator SVCDVC,NVO1+VO1SVCVSPDVRNL-DACVO1+VO1 SVCDAQ10VSPDVRNL-DACSVCDVC,NDVC,PDVC1010NMOS VCPMOS VCComplementary VCPMOS VCDouble-tail Comparator SVCVSPDVRNL-
281、DACVO1+VO1 SVCDVC,PVO1+VO1SVCImplementation of Complementary VC Double-tail comparators with a complementary architecture Using the MSB of DAQto determine the proper VC Only one VC operates at once No additional power consumption10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling P
282、LLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference23 of 29Die Photograph 40nm CMOS Power:15.3mW Area:0.17mm2TotalPower Consumption(mW)LC-VCO+Buffer11.5Digital Logic+P&I-Path1.215.3MMD+ResamplerSPD&RNL-DAC1.6Complementary VC0.2Fine-DTC0.60.210.5:A 76f
283、srms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference24 of 29fOUT=11.100293GHzSOUT:RMS Jitter=76fsPower(dBm)506070904030201065dBc293kHz507090110130Phase Noise(dBc/Hz)15080Measured PLL Output P
284、N&Spectrum Near 11.1GHz Integrated JitterRMS(10kHz 100MHz):76fs Fractional Spur:65dBc10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference25 of 29fOUT=10.500293GHzSOUT:RMS Jitter=74f
285、sPower(dBm)506070904030201065dBc293kHz507090110130Phase Noise(dBc/Hz)15080Measured PLL Output PN&Spectrum Near 10.5GHz Integrated JitterRMS(10kHz 100MHz):74fs Fractional Spur:65dBc10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a Nonlinearity-Replication Technique 2024
286、 IEEE International Solid-State Circuits Conference26 of 2910.50fOUT(GHz)706580JitterRMS(fs)758510.8011.1011.4011.7010.6510.9511.2511.55Measured RMS Jitters Across DINTs Integrated JitterRMS(10kHz 100MHz)across DINT 79fs10.5:A 76fsrms-Jitter and 65dBc-Fractional-Spur Fractional-N Sampling PLLUsing a
287、 Nonlinearity-Replication Technique 2024 IEEE International Solid-State Circuits Conference27 of 29Power(dBm)5060709040302010150MHzReference Spur:67dBcMeasured Spectrum Near 11.1GHz Reference spur 15GHz chirp bandwidth(BWchirp)n 1s chirp duration(Tchirp)l 15GHz/s chirp slopel 50ns Tidle time for 95%
288、duty cyclen Good chirp linearity and Phase NoiseA.Mm-level lateral resolution B.Sub-cm depth resolutionC.Milliseconds snapshot durationD.Better imaging quality An ultra-fast wideband PLL is requiredChirp Waveform TimeFrequency.Tx1TxNTchirpTidle.Snapshot durationBWchirpTx010.7:An 11GHz 2nd-order DPD
289、FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference7 of 61Outlinen Motivationn PLL Architecturen Background Calibration for High Chirp Linearityl2nd-Order Curve Fitti
290、ng(CF)Digital Pre-Distortion(DPD)lPhase-Error Sign Extractionn Zero-Phase-Error DTC Modulatorn System Implementationn Measurement Resultsn Conclusions10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65
291、nm CMOS 2024 IEEE International Solid-State Circuits Conference8 of 61DTC-Based Fractional-N Sub-Sampling PLLn No divider in main loopl Low powern High phase detector gainl Low in-band phase noise n Phase matching with DTC modulatorl Low quantization noiseK.Raczkowski,JSSC15DTCRefmGPCSRSCPFDw/i DZCP
292、MMDBUFVPLLVsampISOBUFLowpass(Phase Mod.)DTC ModulatorDTC CodeFCW0DIV Code10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference9 of 61DTCRefm
293、GPCSRSCPFDw/i DZCPMMDBUFVDACVPLLVsampISOBUFHighpass(Freq.Mod.)Lowpass(Phase Mod.)vdac_codenDTC ModulatorDTC CodeFCW0+MODkDIV CodeVFMTwo-Point Modulation(TPM)n Break the trade-off between PLL BW and chirp slopeMODkKLMODkKHFOUTkn All-pass transfer function for the modulated signalQ.Shi,JSSC1910.7:An 1
294、1GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference10 of 61DTCRefmGPCSRSCPFDw/i DZCPMMDBUFVDACVPLLVsampISOBUFHighpass(Freq.Mod.)Lowpass(Phase Mod.)
295、vdac_codenDTC ModulatorDTC CodeFCW0+MODkDIV CodeVFMTwo-Point Modulation(TPM)n Break the trade-off between PLL BW and chirp slopen Accurate gain matching between two paths is necessary for high linearityMODkKLMODkKHFOUTkn All-pass transfer function for the modulated signalQ.Shi,JSSC1910.7:An 11GHz 2n
296、d-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference11 of 61This Workn Ramp tracker assisted 2nd-CF DPDl Chirp linearity calibrationn Voltage tracking loop
297、(VTL)l Phase-error sign extractionn Zero-phase-error DTC modulatorl Accurate phase matching under large frequency hoppingDTCRefmGPCSRSCPFDw/i DZCPEK_EXTkMMDBUFVDACVPLLRamp Tracker Assisted 2nd-CF DPDVsampISOBUFHighpass(Freq.Mod.)Lowpass(Phase Mod.)vdac_codenZero-Phase-Error DTC ModulatorDTC CodeFCW0
298、+MODkDIV CodeVFMDigitalVoltage Tracking Loop10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference12 of 61Outlinen Motivationn PLL Architectu
299、ren Background Calibration for High Chirp Linearityl2nd-Order Curve Fitting(CF)Digital Pre-Distortion(DPD)lPhase-Error Sign Extractionn Zero-Phase-Error DTC Modulatorn System Implementationn Measurement Resultsn Conclusions10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Err
300、or under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference13 of 61Chirp Nonlinearityn Code-to-Freq Nonlinearity!Code-to-V:IDAC finite impedanceV-to-Cap:Nonlinear varactor Cap-to-Freq:Nonlinear frequency tuning curve of VCO
301、()VDACVFMVPLLVDAC Coden Calibrations are necessary for good chirp linearity10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference14 of 61Prio
302、r Art#1:1st-Order Look-Up Table(LUT)n 1st-order ramp curve fitting with 1st-order LUTQ.Shi,JSSC1910.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits
303、Conference15 of 61Prior Art#2:0th-Order LUT+Ramp IntegratorP.T.Renukaswamy,JSSC20n QDAC:Ramp integratorn 0th-order ramp rate curve fitting with 0th-order LUTn A linear chirp is generated with a ramp integrator10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3
304、GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference16 of 61Issue:Large Residual Frequency Errorn 1st-order LUT or 0th-order LUT+ramp integrator could realize 1st-order curve fitting functionn Works well with slower chirp(Tchirp10
305、s)n Unable to suppress the residual frequency error with finite PLL BW for the ultra-fast wideband chirp generation10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Sol
306、id-State Circuits Conference17 of 61Idea:2nd-Order Curve Fitting DPDn Smaller residual frequency errorn How to realize?Proposed 2nd-order curve fittingstep_calfcw_scalevdac_code_errorfcw_scalefcw_scalevdac_codeSmall residual error10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Freque
307、ncy Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference18 of 61Solution#1:2nd-Order LUTn Direct ramp fitting with 2nd-order LUTThe chirp linearity is improved with 2nd-CF DPDHigh hardware complexity and longer co
308、nvergence timeEK_EXTk2-K10115.0115.c0c1c15qck2-K20115.0115.b0b1b15qckqfk2-K30115.0115.a0a1a15qckqfkqfkqfk11qfkqfkDcalk10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International
309、Solid-State Circuits Conference19 of 61EK_EXTk2-K10115.0115.c0c1c15qck0115.qckqfk11Ramp Integratorg0g1g15c1-c0c2-c1c15-c14.DcalkSolution#2:1st-Order LUT+Ramp Integratorn Ramp rate fitting with 1st-order LUT+Ramp IntegratorEquivalent function as 2nd-order LUT Lower hardware complexity10.7:An 11GHz 2n
310、d-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference20 of 61EK_EXTk2-K10115.0115.c0c1c15qck0115.qckqfk11Ramp Integratorg0g1g15c1-c0c2-c1c15-c14.DcalkIssue:
311、Convergence Problemn Ramp rate fitting with 1st-order LUT+Ramp IntegratorEquivalent function as 2nd-order LUT Lower hardware complexityThe calculation of gil LUT register ci interacts with each other l Slow down the convergence of LUT and even lead to instabilityThe ramp integrator l Incompletely co
312、nverged ci affects the convergence of following cj10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference21 of 61step_calkEK_EXTkPolarity2-K10
313、115.0115.c0c1c15qck0114.15g0g1g14g15c1-c0c2-c1c15-c14c15-c14.qckqfkfcw_stepPolarityf2v_gainvdac_codenChirp_clr1st-order LUTload to ciRampIntegratorSW_LUTEK_EXTkPolarity2-K2Ramp Trackerslope_rtkfcw_chirpkScale FactorqckqfkQfcw_scalekAddress Scale2nd-order Curve Fitting DPDramp_ratek01EN_LUTRamp Track
314、er(RT)Assisted 2nd-CF DPDn RT and LUT are switched with a multiplexer and enabled in different time slotsn ci could be initialized by ramp tracker to solve the convergence problem10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s S
315、lope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference22 of 61Cooperation Between RT and LUTn Ramp trackingl Configured with slow chirpl 16 coefficients are sampled from slope_rtkl Sampled data are passed to ci in the LUTn LUT calibrationl Configured with fast c
316、hirpl LUT is calibrated with initialized ci20025030035040045050010.010.511.011.512.0chirp freq(GHz)2002503003504004505000.60.81.01.21.41.6Time(s)ramp_rate0.60.81.01.21.41.6ciSW_LUT=0SW_LUT=1ramp tracking(slow chirp)LUT calibration(fast chirp)Ramp tracking cycleLUT calibration cycle10.7:An 11GHz 2nd-
317、order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference23 of 61Cooperation Between RT and LUTslope_rt4812160Sampling PrincipleSamplingfcw_scalefcw_scale4812160t
318、slope_rtTchirpn Ramp trackingl Configured with slow chirpl 16 coefficients are sampled from slope_rtkl Sampled data are passed to ci in the LUTn LUT calibrationl Configured with fast chirpl LUT is calibrated with initialized ci10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency
319、 Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference24 of 61Cooperation Between RT and LUTslope_rt4812160Sampling PrincipleSamplingfcw_scaleLoad to ci fcw_scale4812160tslope_rtTchirpn Ramp trackingl Configured wi
320、th slow chirpl 16 coefficients are sampled from slope_rtkl Sampled data are passed to ci in the LUTn LUT calibrationl Configured with fast chirpl LUT is calibrated with initialized ci10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz
321、/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference25 of 65040045050010.010.511.011.512.0chirp freq(GHz)2002503003504004505000.60.81.01.21.41.6Time(s)ramp_rate0.60.81.01.21.41.6ciSW_LUT=0SW_LUT=1ramp tracking(slow chirp)LUT calibration(fast chi
322、rp)Cooperation Between RT and LUTn Ramp trackingl Configured with slow chirpl 16 coefficients are sampled from slope_rtkl Sampled data are passed to ci in the LUTn LUT calibrationl Configured with fast chirpl LUT is calibrated with initialized ciRamp tracking cycleLUT calibration cycle10.7:An 11GHz
323、2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference26 of 65040045050010.010.511.011.512.0chirp freq(GHz)2002503003504004505000.60.81.01.21.41
324、.6Time(s)ramp_rate0.60.81.01.21.41.6ciSW_LUT=0SW_LUT=1ramp tracking(slow chirp)LUT calibration(fast chirp)Cooperation Between RT and LUTn Ramp trackingl Configured with slow chirpl 16 coefficients are sampled from slope_rtkl Sampled data are passed to ci in the LUTn LUT calibrationl Configured with
325、fast chirpl LUT is calibrated with initialized ciRamp tracking cycleLUT calibration cyclen Reliable convergence10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-S
326、tate Circuits Conference27 of 61Outlinen Motivationn PLL Architecturen Background Calibration for High Chirp Linearityl2nd-Order Curve Fitting(CF)Digital Pre-Distortion(DPD)lPhase-Error Sign Extractionn Zero-Phase-Error DTC Modulatorn System Implementationn Measurement Resultsn Conclusions10.7:An 11
327、GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference28 of 61Phase-Error Sign Extractionn Phase-error sign could not be directly extracted from the SS
328、PLLn Additional sign extractor is needed for background calibrationDTCRefmGPCSRSCPFDw/i DZCPEK_EXTkMMDBUFVDACVPLLRamp Tracker Assisted 2nd-CF DPDVsampISOBUFHighpass(Freq.Mod.)Lowpass(Phase Mod.)vdac_codenDTC ModulatorDTC CodeFCW0+MODkDIV CodeVFMDigitalSign ExtractorSignal from SSPLL10.7:An 11GHz 2nd
329、-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference29 of 61Prior Art#1:Current-Mode Sign Extractorn Sign-error is extracted from the current direction of G
330、m n The input offset of comparator would cause calibration inaccuracies in LUTQ.Shi,JSSC19Vcmp_os10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits
331、Conference30 of 61Prior Art#2:Voltage-Mode Sign ExtractorW.Wu,JSSC19DTCRefmGMMDDTC ModulatorDTC CodeFCW0DIV CodeVsampVref+-SPDLPFEK_EXTkDSMVtmpDACVcmp_osVGm_osVoltage Tracking LoopCMP_CLKn Phase-error sign could be detected by extracting Vsamp of sampling phase detector(SPD)n Circuits offsets(VGm_os
332、 and Vcmp_os)could be eliminated with VTL10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2.3GHz Chirp Bandwidth,2.3GHz/s Slope,and 50ns Idle Time in 65nm CMOS 2024 IEEE International Solid-State Circuits Conference31 of 61Prior Art#2:Voltage-Mode Sign Extracto
333、rn Phase-error sign could be detected by extracting Vsamp of sampling phase detector(SPD)n Circuits offsets(VGm_os and Vcmp_os)could be eliminated with VTLn Kickback may be an issueW.Wu,JSSC19DTCRefmGMMDDTC ModulatorDTC CodeFCW0DIV CodeVsampVref+-SPDLPFEK_EXTkDSMVtmpDACVcmp_osVGm_osVoltage Tracking LoopCMP_CLK10.7:An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%rms Frequency Error under a 2