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1、 v1.0 How Infineon controls and assures the reliability of SiC based power semiconductors Whitepaper 07-2020 How Infineon controls and assures the reliability of SiC based power semiconductors 2 07-2020 Table of contents 1 Introduction 3 2 Why do SiC based devices require some additional and differe
2、nt reliability tests compared to Si based devices? 4 3 Gate-oxide reliability of industrial SiC MOSFETs FIT rates and lifetime 5 3.1 Introduction to gate oxide reliability for SiC MOSFETs 5 3.2 Basic aspects of SiC MOSFET gate-oxide reliability screening 5 3.3 Stress tests for extrinsic gate-oxide r
3、eliability evaluation 7 3.3.1 Marathon stress test 7 3.3.2 Gate voltage step-stress test 9 3.4 Conclusions 10 4 Gate-oxide reliability of industrial SiC MOSFETs Bias Temperature Instabilities (BTI) 11 4.1 Parameter variations of SiC MOSFETs under constant gate bias conditions (DC BTI) 11 4.1.1 Intro
4、duction to DC BTI 11 4.1.2 Measuring DC BTI in SiC power devices 12 4.1.3 Comparison of DC BTI in SiC and Si power MOSFETs 13 4.2 Parameter variations of SiC MOSFETs under real world application gate switching operating conditions (AC BTI) 16 4.2.1 Introduction 16 4.2.2 AC BTI modelling 17 4.2.3 Bas
5、ic characteristics of AC BTI 18 5 Silicon carbide cosmic ray robustness 22 6 Short circuit ruggedness of CoolSiC MOSFETs 26 7 SiC body diode bipolar degradation 28 7.1 Mechanism 28 7.2 Effects in the application 29 7.3 CoolSiC MOSFET strategy to eliminate the risk 29 8 Qualification at the product l
6、evel 30 8.1 Testing beyond todays standards according to real world mission profiles 30 8.2 AC-HTC test procedure 33 8.3 Power cycling seconds 34 8.4 Long-term application tests 35 9 Automotive qualification: an approach beyond the standard 36 9.1 Higher field reliability for automotive SiC customer
7、s 38 9.2 No compromises on robustness against humidity for automotive parts 39 10 Industry standards for SiC device reliability and qualification 41 How Infineon controls and assures the reliability of SiC based power semiconductors 3 07-2020 1 Introduction Infineons CoolSiC trench based silicon car
8、bide power MOSFETs represent a dramatic improvement in power conversion switching device Figure Of Merit (FOM) values with outstanding system performance. This enables higher efficiency, power density and reduced system cost in many applications. This technology can also be considered as being an en
9、abler for new applications and topologies. However, as with all new technologies, it is essential that a thorough technology development and product qualification procedure is followed. Only in this way can design lifetime and quality requirements for power conversion systems be achieved. Despite th
10、e similarities to silicon, e.g. the vertical device structures, the presence of a native oxide like SiO2 or the majority of processing steps, there are still important differences related to the material properties itself and the operating modes of these new power devices. As these differences are s
11、ubstantial, their impact on the operation in the final application and on the required development and reliability qualification processes must be carefully considered. This paper describes the major steps in the release process that Infineon has used to successfully qualify CoolSiC technology and p
12、roducts. Key failure mechanisms are described, and the means to ensure safe and reliable operation in a wide variety of applications are provided. Through this approach, many risks our customers would otherwise encounter are avoided and a safe path to the reliable use of Infineon CoolSiC technology
13、is provided. This publication also holds tutorial value to engineers with an interest in better understanding silicon carbide related reliability. How Infineon controls and assures the reliability of SiC based power semiconductors 4 07-2020 2 Why do SiC based devices require some additional and diff
14、erent reliability tests compared to Si based devices? One of the success factors of implementing SiC as a power device material is the chance to adopt many of the well known device concepts and processing technologies from silicon. Among those are the basic device designs like vertical Schottky diod
15、es or vertical power MOSFETs (after some detours via JFETs and BJTs as alternative structures). Thus, many of the procedures used to verify the long term stability of silicon devices could be transferred to SiC. Nevertheless a deeper analysis has shown that SiC based devices require some additional
16、and different reliability tests compared to Si based devices. The major items which turned out to be relevant are the following: The material itself with its specific defect structures, anisotropies, mechanical and thermal properties etc. The larger bandgap with its implications on the density and d
17、ynamics of interface traps in MOS based devices Up to about 10 x higher electrical fields in operation within the material itself and at the outside interfaces, e.g. device edges (including new edge termination designs), plus its impact on oxide lifetime New operating modes where high voltage operat
18、ion (VDS 1000 V) and fast switching ( 50 V/ns) are combined The listed items may have an influence on nearly all established qualification tests. Power cycling second tests will lead to different results due to different mechanical properties. Contrary to silicon based power devices the setup of oxi
19、de reliability tests for SiC have to also cover stability in blocking mode. Furthermore, for many existing qualification standards that specify accelerated tests, models are used to extrapolate the test data and correlate it to real world application conditions. These model parameters need to be ver
20、ified for their application and accuracy with respect to SiC. Infineon has intensely analyzed all of these items over the last 25 years during the development and production of SiC based power devices. New tests have been developed to address different operating modes not seen by silicon power semic
21、onductors and other tests have been modified to take into account SiC specific requirements. It is important to emphasize, that key parts of the characterization and validation scheme are based on a mission profile based stress analysis. This was done in order to assess the critical operating condit
22、ions for SiC devices and to understand new potential failure mechanisms. The details are described in the following chapters. How Infineon controls and assures the reliability of SiC based power semiconductors 5 07-2020 3 Gate-oxide reliability of industrial SiC MOSFETs FIT rates and lifetime 3.1 In
23、troduction to gate oxide reliability for SiC MOSFETs High numbers of early gate-oxide failures have hampered the commercialization of SiC MOSFETs for many years, and provoked skepticism whether SiC MOS switches would ever be as reliable as their Si counterparts. During the last decade, SiC technolog
24、y has substantially matured and SiC MOS devices have exhibited gradual improvements in gate-oxide reliability. This has opened the door for their successful introduction into the mass market. In the field of gate-oxide reliability, there is a lot of expertise that can be reused from Si technology. F
25、or instance, it was shown that the physical breakdown strength of SiO2 on SiC is similar, if not identical, to SiO2 on Si 1. This means that the overall breakdown stability of SiO2 fabricated on SiC is as good as SiO2 fabricated on Si. The shortcoming in gate-oxide reliability of SiC MOSFETs with re
26、spect to Si MOSFETs is due to “extrinsic” defects. Extrinsic defects are tiny distortions in the gate-oxide, which act as local oxide thinning, cf. Figure 1. Figure 1 Schematic representation of extrinsic defects in SiO2. Extrinsic defects can be physical oxide thinning due to, for instance, a disto
27、rted oxide on top of an EPI/substrate defect or electrical oxide thinning caused by a degraded dielectric field strength due to inclusions of metallic impurities, particles or porosity 2. Such distortions may originate from EPI or substrate defects 2, metallic impurities, particles or other extrinsi
28、c inclusions in the gate-oxide incorporated during device fabrication. 3.2 Basic aspects of SiC MOSFET gate-oxide reliability screening At the end of processing, gate-oxides fabricated on SiC have typically a much higher early failure probability because they exhibit higher numbers of extrinsic defe
29、cts, cf. Figure 2. How Infineon controls and assures the reliability of SiC based power semiconductors 6 07-2020 Figure 2 Schematic representation of the extrinsic and intrinsic Weibull distributions for SiC MOSFETs and Si MOSFETs having the same oxide thickness and area. F depicts the cumulative fa
30、ilure probability, t the time. Due to a higher electrical defect density, SiC MOSFETs exhibit 3-4 orders of magnitude higher extrinsic defect densities in the gate- oxide. The chip lifetime is the time the device has to survive in the application under normal use conditions. To make SiC MOSFETs as r
31、eliable as their Si counterparts, the gate-oxide defect density has to be minimized during processing. Additionally, innovative screening techniques, to identify and eliminate potentially weak devices, e.g. in the electrical end test, have to be developed. The screening of weak devices in the end te
32、st is typically done by subjecting each device to a high gate-voltage stress pulse with defined amplitude and time 3 4. The stress pulse is designed to identify devices with critical extrinsic defects while devices without extrinsic defects or with only non-critical extrinsic defects survive. The re
33、maining surviving, screened, population shows a significantly improved gate-oxide reliability 5. The enabler for a fast and efficient gate-voltage screening is a much thicker bulk-oxide layer than what is typically needed to fulfill intrinsic lifetime-targets. The thicker bulk-oxide layer allows the
34、 use of screening voltages much higher than the typical device use-voltage without degradation of non-defective devices which are passing the screening test. The higher the screening voltage to the use-voltage ratio, the more efficient the electrical screening 6. By eliminating defective devices in
35、the end test a potential reliability issue for the customer is converted to a minor yield loss for the device manufacturer. SiC MOSFETs that pass our screening test show the same excellent level of gate-oxide reliability as Si MOSFETs or IGBTs 7. The downside of a thicker bulk-oxide layer is a sligh
36、tly higher MOS channel resistance. The MOS channel resistance is directly proportional to the gate-oxide thickness and can be a major portion of the total on-resistance, in particular, for devices of lower voltage classes that provide a comparatively small drift-zone resistance. Ultimately, high scr
37、eening efficiency, and hence excellent gate-oxide reliability of SiC MOSFETs, is not entirely for free, but comes at the cost of a slightly increased on-resistance. This design trade-off between reliability and performance is inevitable, however, it is possible to take advantage of the fact that on-
38、resistance and gate oxide reliability show a different dependence on bulk oxide thickness. SiC MOSFET () Si MOSFET -6 -2 intrinsic branch extrinsic branch chip lifetime uncritical critical (1 ) How Infineon controls and assures the reliability of SiC based power semiconductors 7 07-2020 While gate o
39、xide reliability improves exponentially with oxide thickness, the on-resistance increase is only linear. At elevated temperatures, where the drift-zone resistance is more pronounced, the performance penalty is even smaller in relative numbers. To summarize, by sacrificing just a little performance b
40、y using a thicker bulk-oxide layer leads to a strong gain in reliability. Infineon decided, from the beginning, to use a Trench based MOSFET technology. The reason for this is that trench based devices, compared to planar devices, have significantly higher channel conductivities at low electric fiel
41、ds across the gate oxide during on-state of a MOSFET as the penalty of a thick oxide layer. A not very attractive alternative to gate voltage screening at high screening voltages and room temperature is the classic burn-in test. During burn-in devices are typically stressed at somewhat lower gate vo
42、ltages and elevated temperatures for much longer times. This approach has several disadvantages. A burn-in is time-consuming, costly, and may cause severe drift of threshold voltage and on-resistance due to long-lasting gate stress at high bias and high temperature, which is known to trigger bias te
43、mperature instabilities 8. 3.3 Stress tests for extrinsic gate-oxide reliability evaluation To make reliable predictions about failure probabilities under normal device operation conditions, it is mandatory to perform stress tests that explore the early breakdown regime of device failure 9. Stress t
44、ests aiming to explore the oxide wear-out regime, such as highly accelerated Time-Dependent- Dielectric-Breakdown (TDDB) tests which are typically performed only on a small number of samples, are not appropriate to study failures that may happen during normal device operation (voltage, temperature)
45、within typical chip lifetimes. To overcome this problem, Infineon developed two different stress test approaches to verify the screening and thereby the gate oxide reliability for all devices. 3.3.1 Marathon stress test A common approach to study extrinsic failures is to stress devices as close as p
46、ossible to the real world application conditions and at the same time test large numbers of samples. Large sample sizes are required because extrinsic failures are usually rare, in particular, after electrical screening. For this purpose, we have developed a new kind of test procedure, which we call
47、 the “marathon stress test” 5. In this test, thousands of devices are stressed in parallel in a parameter range close to operating conditions and comparable to typical burn-in conditions. However, contrary to burn-in, we use much longer stress times (100 days) in order to increase the probability to
48、 find extrinsic failures. To manage the large sample quantities required for the marathon stress test, we have developed a special test setup in which we put multiple devices in one package, many packages on one stress board and several stress boards into one furnace. Multiple furnaces are can be op
49、erated in parallel. In a case study, we have performed three independent marathon test runs on three sample groups of electrically screened devices with different extrinsic defect densities. The three groups roughly align with the progress made during the device development phase, namely group 1 corresponds to the initial stage of oxide process development while group 3 represents the technology status shortly before How Infineon controls and assu