《Accelerating infrastructure with Data Processing Units.pdf》由会员分享,可在线阅读,更多相关《Accelerating infrastructure with Data Processing Units.pdf(15页珍藏版)》请在三个皮匠报告上搜索。
1、Accelerating Infrastructure with Data Processing Units(DPU)IT Ecosystem:NetworkingAccelerating Infrastructure with Data Processing Units(DPU)Biren MehtaDirector,Network&Edge InfrastructureArmArm Technology is Defining the Future of ComputingA semiconductor design and software platform company Active
2、 licensees,growing by 50+every year.650+Arm-based chips shipped in FY 2021.29.2 BillionArm-based chips shipped to date.240 BillionThe global leader in the development of licensable compute technologyArms energy-efficient processor designs&software platformsenable advanced computingArm delivers the f
3、oundational buildingblocks for trust in the digital worldThe Problem StatementEnding of Moores Law Single Core performance is plateauing Network I/O growing exponentially Rising SoC costs Single-core performanceMarket ChallengesIneffective handling of Data Centric WLsWeak Security Resource SilosInfr
4、astructure Architecture Inefficiencies We must rethink the computing infrastructure Data-Centric Architecture RequirementsData Centric ArchitectureEfficiently process high bandwidth workloadsOptimized multiplexing and task switching between WLs(Network,Security,Storage,etc.)Augment efficient compute
5、 complex with domain specific acceleratorsInfrastructure&Tenant SeparationDecoupling of infrastructure processing from business application for tighter security Tenants fully control the CPU with their SW,while infra provider maintain control of the infrastructure and root of trust Optimized TCORedu
6、ction in SoC costs with Heterogenous compute Offload infrastructure for expensive host CPU and minimize latency/jitter.Composable Infrastructure Cloud like orchestration of infra resources(CPU,G PU,Storage,Memory,etc).Simplify data center architectureEnable disaggregated device pools(GPU,Memory,Stor
7、age,etc.)Rise of Domain Specific Accelerator to Address Data Heavy WorkloadsData-Centric Architecture RequirementsCloud Like Composable Infrastructure NICCPUComputecentricarchitectureNetworkSSDGPUDRAMHDDRAMFPGADRAM CPU:Application&Infra WLs GPU,FPGA:highly matrixed/programmable AppsDatacentricarchit
8、ectureDPUDPUDPUDPUDPUDPUDPUDPUCPU,GPU,SSD,DRAMCPU,GPU,SSD,DRAMCPU,GPU,SSD,DRAMCPU,GPU,SSD,DRAMCPU,GPU,SSD,DRAMCPU,GPU,SSD,DRAMCPU,GPU,SSD,DRAMCPU,GPU,SSD,DRAMOptimized processing of Data Heavy WLTighter SecurityMinimize Latency/JitterComposable InfraDeconstructing DPUA micro-server optimizedfor data
9、flowandpacket processingprovidingaccelerators,offloadengines,andlocalservicesSwitchNICNICNICNICPCIeMgtBMCNICAcceleratorsArm CoresP4PipelinesDPUNetworking:NAT,LB,QOS Scheduling,EncryptionStorage:CompressionEncryptionDataDedupSecurity:IPS/IDSNGFW,ROTMacSEC/IPSec/TLSServerGPUNVMeBMCDirectAccessPCIeSide
10、band InterfaceDPUHostingSystemPersistent memoryDRAMCPUCore Compute RolesCores as orchestratorsProcessing done in special acceleratorsCores co-ordinate jobsPipeline of accelerators stitched as per use-caseCores in data-pathProcessing mix of cores+acceleratorsPipeline mapped as per system capabilities
11、.Generic coreRTL LogicAcceleratorsAcceleratorsAcceleratorsAcceleratorsGeneric coreGeneric coreRTL LogicAcceleratorsGeneric coreGeneric coreAcceleratorsMix of custom-cores,RTL+acceleratorsProcessing pipeline mostly pre-definedP4 as common programming modelCustom-coreRTL LogicCustom-coreCustom-coreAcc
12、eleratorsAcceleratorsAcceleratorsCustomcoreAcceleratorsCores for assistCore functions in RTLCores offload/assist extend functionalityRTL LogicGeneric coreGeneric coreAcceleratorsLeading DPU Vendors Powered by Arm60%higher PPS,30%lower latency,40%better Perf/WIntel Mount Evans IPU 16 x N1 coresMarvel
13、l Octeon 10 DPUUp to 36 x N2 coresNvidia DPUBF3:16 x A78 coresBF2:8 x A72 coresPensando DSC-100Up to 8 x A72 coresMarket Availability:TodayArm Neoverse Software Ecosystem 100+ISVs100s of OSS Projects200K+CI/CD Build Minutes per Month1M+Docker Hub Images Widest possible choice of Platforms Performanc
14、eEfficiencyBest$/throughput in the industryPlatform DiversityOptimizationPurpose built use cases Scalable Neoverse CPU Cores Native BuildCommercial SupportOSS Enablement&Optimization by ArmLinuxTrusted FirmwareC/C+ToolchainsGo.NETJavaNode.JSRustPHPTensorFlowXLASNOW CiphersOpenSSLSnappyVectorScanZLib
15、IPSEC-MBApache BigTopMySQLKata ContainersCloud-HypervisorgVisorKubernetesKubeVirtISA-LSPDKCephMachine LearningOptimized LibrariesStorage and DataContainersCloud LanguagesPyTorchArm Compute LibraryVPPDPDKODPLZ45G RALebpfCreate a common framework for DPUs to extend existing OSS projectsPossible inters
16、ection with OCP to explore:OCP Hardware co-designDASH&SAIDC-MHSOpen Accelerator InfrastructureComputational StorageComposable memory systemOPI:where OCP Projects meet DPUsOpen Programmable Infrastructure(OPI)Create community-driven standards-based open ecosystem for DPU/IPU-like technologiesCreate v
17、endor agnostic framework and architecture for DPU/IPU-based software stacksReuse existing or define a set of new common APIs for DPU/IPU-like technologies when requiredProvide implementation examples to validate the architectures/APIsCPUNICUSER APPLICATION/WORKLOADNETWORKSTORAGEMgmt&Security.Baremet
18、al OS/Container Platform/(Partitioning)HypervisorDedicated ProcessorHW Accelerators/Offload EnginesPCIeDPU/IPU-like device Baremetal OS/Container Platform/HypervisorSW SUBSYSTEMOOBM/BMCArm will be part of the OPI journeyCollaborate with usNorth Americas first OCP Experience Center,hosted by Arm,to a
19、ccelerate and enable collaboration within Arm ecosystem to drive Arm SystemReadySR certified and OCP Accepted,OCP Inspiredserver hardwareLocated in New Jersey,the experience center is fully operational and Arm ecosystem partners and OCP Community members can participate starting todayocp-Join us in the OPI project and align OCP initiatives with standard,open community focused on accelerating adoption for DPU technologies.Open Discussion