《Known Good Die (KGD) for Chiplet Based Heterogenous Integration.pdf》由会员分享,可在线阅读,更多相关《Known Good Die (KGD) for Chiplet Based Heterogenous Integration.pdf(14页珍藏版)》请在三个皮匠报告上搜索。
1、Known Good Die(KGD)For ChipletsBased Heterogeneous Integration Yogan SenthilkumarChipletsKnown Good Die(KGD)For Chiplets Based Heterogeneous Integration Yogan Senthilkumar,Vice President Engineering,Tessolve SemiconductorAgendaIs KGD a new thing?What is the significance of KGD from Chiplet perspecti
2、ve.KGD MonitoringTraceability of KGDActual Use Case Test Leading to System Level Test in volume productionTest Flow for ChipletsBased IC.SummaryIs KGD a new thing?Dies are tested before being packaged.KGD has been there for may decades.Assembly defects and functionality at speed are tested at packag
3、e level.Third party Die could be integrated .such as HBM/SERDESIn Monolithic integration the functional requirement of the packaged parts do not change drastically from the Die level.KGD for Heterogenous IC Package Individual Die not necessarily define the full functionality of the Packaged IC.could
4、 be only partial.DPPM control is much with in the product company control.Assembly defects after package of a particular KGD many not be 100%directly detectable Additional test.Individual Die DPPM come into picture.The over all package level DPPM becomes additive of individual KGD DPPMWhat is the si
5、gnificance of KGD from Chipletsperspective.Die to die interconnect within the package only going to be in millimeters.Test times of the individual Die on ATE would be in seconds.Decision of pass or fail as KGD to be taken by then.Loop back test might very much applicable for High-Speed Interface Rea
6、lity of SI Simulation on Substrate interconnect vs actual manufactured substrate cannot be assumed to matchTight manufacturing tolerance of Line width,space etc.is critical.Net list Open/Short test of substrate+Critical hi speed substrate trace testing on sampling would help to improve packed IC yie
7、ld.Possibility of Critical signal trace coupon can be explored.KGD Test Limit Gaurd band keeping in account of Heterogeneous IC Package What is the significance of KGD from Chipletsperspective.Package Level failure that points to a specific Chiplet-configuration needs “next lower graded Device”.In t
8、he event failed Die replacemet not possible.DFT architecture need to be implemented as Sub-Block approach.So that the Scan vectors could be still run by isolating the faulty Sub-Block/Chiplet and still able to verify the remaining integration.SSN/1149.10 based DFT architecture would need to be explo
9、redImage courtesy :IEEE Computer SocietyKGD MonitoringWhat is happening inside the Chip?Monitor(Design,Volume Test and In-Field)In-Chip-Monitor Instantaneous Environmental Monitor.Process Monitor.Power Rail Voltage Monitor.Temperature Monitor.Process Monitor-Behavioral understanding of Wafer Level a
10、nd Lot Level Power Rail Voltage Monitor-Compute Performance optimization by monitoring Voltage-Alarm/Interrupt Signal activation to other subsystem and bring the device to safe state-Could be considered as a part of POST Temperature Monitor-Compute Performance optimization by monitoring Temperature-
11、Alarm/Interrupt Signal activation to other subsystem and bring the device to safe state-Could be considered as a part of POST and Mission Mode Test.KGD MonitoringSeems no SLM Standards established yet!In-Chip-Monitor Structural Monitor Semiconductor do have aging as inherent property as it is influe
12、nced by NBTI(Negative Bias Temperature Instability),HCI(Hot Carrier Injection)and TDDB(Time dependent dielectric breakdown).Aging affecting Propagation DelayPath Margin MonitoringEDA Vendors now provide Silicon Life Management Tool(SLM)for end-to-end Visibility.Right from Design,Product Ramp,Volume
13、Production and finally In-FieldTraceability of KGDWhat happens when the Heterogenous packaged IC Fails in the Field?InfantNormal LifeEOLYearsTraceability ImportanceAssembly DataTest DataWafer IDDie IDOSAT provide Unit Level Traceability(ULT)by 2d Barcode on a Packed DeviceCommercial Device may need
14、about 5 years of traceability but for Automotive it would extend to 15 YearsIdentifying root cause sooner would be important for Automotive Grade IC(especially for ADAS Levels 4 and 5)and probably for high end HPC ICs Standardizing traceability for Chiplet Based Heterogenous IC Packed at Individual
15、Diel level and exchange of information form the Packaged IC on a established Interface protocol.Thus,enabling Datal Analytics need to considered of ImportanceSEMI Traceability Standards committee SEMI T23Actual Use Case Test Leading to System Level Test System-level test is the ability to test a chi
16、p,or multiple chips in a package,in the context of how it ultimately will be used.*Source:Semiconductor Engineering 9 Oct 2017ATE test focus more on getting the various blocks that are present within the IC tested for a pass and fail and classify the device a pass,when all the blocks in the device p
17、assComplex IC used forHPC,Automotive etc.needs to betested along with the other supportive ICs such as PMIC,External Memory,Display,and other power electronic andrunning on a customer-specific firmware.It is important tomention that the external support ICs mentioned may not befrom the same manufact
18、urer.Testing for customer-specific Use Case is becoming a key need for the devices that are used for mission-critical applications such as Automotive and Data Centers(Silent Data Corruption)along with the need for DPPM quality levels drives SLT requirementSLT is performed in massive parallelism in 1
19、00s of Device tested in Parallel and hence a specialized SLT Handler Equipment needed.Additional CapexTest Flow for Chiplet Based ICChiplet 1Chiplet 2Chiplet 3Bumped Die ATE TestBumped Die ATE TestBumped Die ATE TestPackaged IC ATE TestSLTOptional ATE TestShip to customerATE-Parallelism more than 8
20、Package Substrate performance Hi End ATE Parallelism 4 to 8 Single Site SLT for NPI-Use existing HandlerHi Parallelism SLT for Volume SLT HandlerSummary Chiplet I/O being optimized for required drive strength for few mm D2D interconnect Loop back test might very much applicable for High-Speed Interf
21、ace KGD Test Limit Guard band keeping in account of Heterogeneous IC Package The over all package level DPPM becomes additive of individual KGD in the Heterogeneous IC Package In Chip Monitoring and Die level traceability System Level Test Running actual Use Case Test ChipletDFT Architecture considering Heterogeneous Integration.https:/opencomputeproject.github.io/ODSA-BoW/bow_specification.html https:/www.uciexpress.org/specification https:/ and AcknowledgementsThank you!