《SNIA-SDC23-Handy-Coughlin-Riding-Tail-of-Optanes-Comet.pdf》由会员分享,可在线阅读,更多相关《SNIA-SDC23-Handy-Coughlin-Riding-Tail-of-Optanes-Comet.pdf(36页珍藏版)》请在三个皮匠报告上搜索。
1、1|2023 SNIA.All Rights Reserved.Virtual ConferenceSeptember 28-29,2021Riding the Long Tail of Optanes CometEmerging Memories,CXL,UCIe,and MoreJim Handy,Objective Analysis2|2023 SNIA.All Rights Reserved.AgendaOptanes brief historyTodays AlternativesOptanes LegacyCXLUCIeFuture Thoughts3|2023 SNIA.All
2、Rights Reserved.An Optane Timeline“Optane Memory”Discontinued“Optane Memory”LaunchFirst Processor Support of Optane DIMM20002120223D XPoint AnnouncedFirst Optane SSD ShippedFirst Optane DIMM ShippedOptane Consumer SSDs DiscontinuedOptane To“Wind Down”QuantX AnnouncedFirst Quant
3、X SSD DemonstratedMicron Ends Intel RelationshipMicron Kills 3D XPoint EffortMicron Sells Lehi Fab4|2021 Storage Developer Conference.Insert Company Name Here.All Rights Reserved.Todays Alternatives5|2023 SNIA.All Rights Reserved.Alternatives to OptanePersistent?SpeedCost/DRAM IssuesOptaneYes30%50%W
4、inding DownNVDIMM-NYes100%200%Battery/CapacitorMRAM DIMMYes100%1,000%CompatibilityFast SSDYes0.1%20%SlowAdded DRAMNo100%100%+Bus loading6|2023 SNIA.All Rights Reserved.Optanes Still AroundCurrent inventory fulfilling needsOngoing low-level demandSupport already in place7|2023 SNIA.All Rights Reserve
5、d.NVDIMM-NFaster than Optane2X the cost of DRAMRequires back-up power source8|2023 SNIA.All Rights Reserved.MRAM DIMMProduction started in 2017DDR3 onlyRequires changes to processor100X the cost of DRAM9|2023 SNIA.All Rights Reserved.MRAM Is Already in the EnterpriseIBM FlashCore Modules use MRAM in
6、stead of DRAM Store translation tables Buffers for write coalescing etc.Easy way to protect data in flight Fast path to persistenceConsumer adoption is growing Wearables,vehicles,health monitors,etc.Drives growing wafer volume Economies of scale will reduce prices10|2023 SNIA.All Rights Reserved.Fas
7、t SSDSSD?Really?Kioxia and Samsung both advocate this Special NAND chip architectures Uses SLC NAND 6X the price of TLC NANDWhich performs better:Fast&Small(DRAM)or Slow&Big(NAND)?11|2023 SNIA.All Rights Reserved.Conundrum:Fast&Small,or Slow&Big?Share of AccessesAddress Range12|2023 SNIA.All Rights
8、Reserved.Its Getting Harder To Add More DRAM“Fast&Small”includes large DRAM approaches But large DRAMs increase loading,slowing the memory channel Adding memory channels increases processor power&pin count This is a thorny problem!IBM has been wrestling with this for years POWER architecture uses bu
9、ffered DIMMs with non-DDR interface OpenCAPI led to the OMI interface CXL is adding slower memory to the CXL channel Disaggregated memory Memory tiering Will discuss this shortly13|2023 SNIA.All Rights Reserved.The Short Story:There Are Many OptionsPersistent?SpeedCost/DRAM IssuesOptaneYes30%50%Wind
10、ing DownNVDIMM-NYes100%200%Battery/CapacitorMRAM DIMMYes100%1,000%CompatibilityFast SSDYes0.1%20%SlowAdded DRAMNo100%100%+Bus loading14|2021 Storage Developer Conference.Insert Company Name Here.All Rights Reserved.Optanes Legacy15|2023 SNIA.All Rights Reserved.Optanes Legacy:New Programming ModelsS
11、NIA NVM Programming Model is just the startHierarchical memory tiers(HBM,DDR,CXL)Memory disaggregation is coming Reduces“Stranded Memory”Models may move into the chiplet Persistent cache(with an emerging memory)16|2023 SNIA.All Rights Reserved.OLD WAYAll DRAM,all one speedPersistence is a storage th
12、ing Slowed by context switchesMemory is only put on the memory channelOnly memory is put on the memory channelNEW WAYMixed memories,mixed speedsPersistence OK in memory No context switches4 channels:HBM,DDR,CXL,&UCIeMemory-Semantic SSDs on CXLOptanes Legacy:A Fresh Look at Memory17|2023 SNIA.All Rig
13、hts Reserved.New Thoughts on Context SwitchesLatency BudgetsNUMAContextSwitch Polling used when a context switch would be too slowPersistentMemory18|2021 Storage Developer Conference.Insert Company Name Here.All Rights Reserved.CXL19|2023 SNIA.All Rights Reserved.DDR-T:Intels Original Approach to Sl
14、ower MemoryDDR-T for OptaneHandles both fast&slow memory Transactional protocol supports slow writesBased on standard DDR4 interface“Modified Control Signals”added to unassigned pins All timing,signaling,protocol otherwise unmodifiedDRAM and Optane share the same sockets Optane and DRAM modules look
15、 nearly identical to the end userMigration from DDR4 to DDR5 a colossal headache!20|2023 SNIA.All Rights Reserved.CXL Solves Multiple ProblemsRemoves processors DDR limitation A processor could use DDR4 or DDR5,but not both CXL allows far memory to use any interface With OMI near memory becomes simi
16、larly independentSupports memory disaggregation No“Stranded Memory”Memory pools can be dynamically allocated Data sets can be moved from processor to processorPaves the way for UCIe21|2023 SNIA.All Rights Reserved.Any Memory Talks to Any ServerDDR4 ServerDDR5 ServerDDR4 DRAMDDR5 DRAMMRAMReRAMFRAMFla
17、shSwitch22|2023 SNIA.All Rights Reserved.CXL 3.0 Supports Memory FabricsNear Memory at CPUFar Memory on CXLCXL to support multiple Far Memory configurations Large Memory Memory Pools Memory Sharing Used for trading messages Memory FabricsNo memory interface dependencies23|2021 Storage Developer Conf
18、erence.Insert Company Name Here.All Rights Reserved.UCIe24|2023 SNIA.All Rights Reserved.UCIe is CXL for Chiplets25|2023 SNIA.All Rights Reserved.A Standardized Chiplet InterfaceSupports multiple sources,and multiple customers26|2023 SNIA.All Rights Reserved.UCIe and MemoriesMixed processes optimize
19、 cost/performance Logic in a CMOS logic process In logic SRAM&NOR flash are the only options for on-die memory Memory chiplet in a memory process DRAM,MRAM,ReRAM,FRAM,PCM Significant die area&cost reductionsCommoditizes chiplets One memory chiplet can be used by multiple logic companies Increases vo
20、lume,lowers costs All vendors parts equivalent Vendors compete on price27|2023 SNIA.All Rights Reserved.SRAM Is No Longer Suited to CMOS Logic SRAM doesnt scale with logic process Cost increases with smaller geometries Emerging memories can solve this problem Future caches will use emerging memories
21、 Larger capacities Cheaper Persistent0f500f1,000f1,500f2,000f2,500f28nm22nm16nm14nm10nm7nm5nm3nmCell AreaProcessSRAM Cell Area(f)vs.ProcessIntelSamsungTSMCSource:Objective AnalysisFrom:Emerging Memories Branch Out28|2023 SNIA.All Rights Reserved.Chiplet Memory Can Be PersistentPersistent code and da
22、ta memory,and even cachesSoftware will need to catch up The SNIA NVM Programming Model is the basis for thisSecurity concerns What if the persistent cache chip falls into the wrong hands?Should cache lines be erased when invalidated?Should all memory communications and NVM data at rest be encrypted?
23、29|2021 Storage Developer Conference.Insert Company Name Here.All Rights Reserved.Future Thoughts30|2023 SNIA.All Rights Reserved.Emerging Memory is Falling Into PlaceLeading-edge processes cant use NOR And SRAM is growing unattractive!Already some use in the enterpriseGrowing adoption in consumer a
24、pplicationsIncreased consumption will reduce prices The economies of scale will accelerate emerging memory penetrationPlus,they offer technical benefits Fast Very low power Less messy than flash31|2023 SNIA.All Rights Reserved.Emerging Memories Are Around the CornerMRAMReRAMFRAMPCM32|2023 SNIA.All R
25、ights Reserved.All New Memories Share Some AttributesSmall single-element cell Supports small/inexpensive die and 3D stacking Promises to scale past DRAM&NAND flashWrite in place No“Block Erase”More symmetrical read/write speedsNonvolatile/Persistent These can all be used as Persistent Memory:“PM”33
26、|2023 SNIA.All Rights Reserved.The Future of Emerging MemoriesEmerging memory revenue forecast to grow significantly faster than DRAM or NAND flashFrom:Emerging Memories Branch Out34|2023 SNIA.All Rights Reserved.New Report:Emerging Memories Branch OutMRAM LineEmergingMemoryvilleToggle ModeVCMRAMRac
27、etrackThermalMeRAMOpto MRAMSpin Branch LineNRAMUltraRAMDistant LineReRAM LineHfO Branch LineFerroelectric LineNOR-Type3D XPointPhase Change Linehttps:/Objective-A SNIA.All Rights Reserved.SummaryOptanes short life founded a great legacy New computing architectures and programming models Many alterna
28、tives for the Optane userCXL has opened the door to new memory architectures Processors no longer tied down to one interface,one memory typeUCIe makes CXLs strengths available to chiplets Chiplets are the path to future processorsEmerging memories are poised to solve tomorrows problems36|2023 SNIA.All Rights Reserved.Please take a moment to rate this session.Your feedback is important to us.