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1、TSN Use Case Modelling for Industrial AutomationPresenterPresenter Su Hea Ming()Ong Boon Leong()Co-authorCo-author Pauline Chan Mei Lan()Donavan Liow Shi Jie()Intel Corporation,Penang,MalaysiaIntel Corporation,Penang,MalaysiaIntel ConfidentialDepartment or Event Name2Embedded World China 20232Our Te
2、amq Su Hea Mingq Solution Architectq IoT Use Case,Customer Solutions,Security and Public Safety q Ong Boon Leongq Principal Software Engineerq Ethernet,TSN,Real-Time,Cloud Native,Linux&Open-Source Softwareq Pauline Chan,Mei Lanq Software Architectq Ethernet,TSN,Telecommunication,Public Safety,q Dona
3、van Liow,Shi Jieq Software Validation Engineerq Ethernet,TSN,IO Sub-systemsIntel ConfidentialDepartment or Event Name3Embedded World China 20233Introduction Industrial networksSensor subsystemController subsystemActuator subsystem Design requires consideration based on Tasks Traffic Load QoS mechani
4、sms System configurationEthernet InterfaceIA-device Sensor subsystem Upper DLL SubsystemsMACPHYIA-Controller subsystem Upper DLL SubsystemsMACPHYIA-device Actuator subsystem Upper DLL SubsystemsMACPHYLevel demandLevel SensorStorage TankControl ValveLevel measured valueActuator outputProcess Interfac
5、eProcessProcessEnd Station End Station ComponentComponentMedia InterfacePHYBridgePHYPHYBridgePHYPHYPHYBridgePHYNetwork Network InfrastructureInfrastructureControl loop inputs(i.e.outputs from sensors)Control loop outputs(i.e.outputs to actuators)LegendIntel ConfidentialDepartment or Event Name4Embed
6、ded World China 20234Industrial Use CaseSeveral IA uses cases are being defined by IEC/IEEE 60802 and also 3GPP,with different traffic profiles.Source:Mahmood,Aamir;Abedin,Source:Mahmood,Aamir;Abedin,SarderSarder Fakhrul;Sauter,Fakhrul;Sauter,ThiloThilo;GidlundGidlund,ikaelikael;LandernsLanderns,Kri
7、sterKrister(2021):Factory 5G:A Review of Industrial-Centric Features and Deployment Options.(2021):Factory 5G:A Review of Industrial-Centric Features and Deployment Options.TechRxivTechRxiv.Preprint.Preprint.Intel ConfidentialDepartment or Event Name5Embedded World China 20235Industrial Use CaseCont
8、rol LoopApplicationApplicationLatency(ms)Latency(ms)D a t a R a t e D a t a R a t e(Mbps)(Mbps)Payload(B)Payload(B)F a c t o r y F a c t o r y automationautomation0.5-2 1-520-250P r o c e s s P r o c e s s automationautomation10 2 20BH M I a n d H M I a n d production ITproduction IT 10 5-2540-250L
9、o g i s t i c s&L o g i s t i c s&warehousewarehouse10 to 100-40-250Monitoring&Monitoring&MaintenanceMaintenanceNon critical,massive devices,energy awareFactories of Future(FoF)Intel ConfidentialDepartment or Event Name6Embedded World China 20236Current Linux TSN MechanismsMulti-Queue Priority(MQPRI
10、O)Multi-Queue Priority(MQPRIO)qdisc:multi-queuing discipline to allow mapping of traffic flows to hardware queues.When using MQPRIO,the application uses socket priority when sorting packets into traffic classes.Each traffic class can then be mapped to a hardware queue.Time Aware Priority(TAPRIO)Time
11、 Aware Priority(TAPRIO)qdisc:Implements the Enhancements for Scheduled Traffic introduced by IEEE 802.1Qbv,which allows configuration of gate states,where each gate state allows outgoing traffic for a subset of traffic classes.TAPRIO qdiscs opens and closes queues based on a user-configurable schedu
12、le entry,allowing for a guaranteed timeslot for each hardware transmit queue.Credit Based Shaper(CBS)qdiscCredit Based Shaper(CBS)qdisc:Implements the Credit Based Shaper functionality in 802.1Qav.CBS is a simple rate limiting shaper to apply bandwidth reservation to user-defined traffic classes.CBS
13、 is installed under another qdisc that maps packet flow to traffic classes,such as MQPRIO and TAPRIO.Earliest TxTime First(ETF qdisc)Earliest TxTime First(ETF qdisc):Implements qdisc in some NICs,such as the Intel i210 network adapter.With ETF,applications can control the time when a packet should b
14、e dequeued from traffic control layer into the network device.Intel ConfidentialDepartment or Event Name7Embedded World China 20237 7 7Design of Experiment IObjectiveObjectiveTo set up a system to measure the latency of IA isochronous traffic using different Linux TSN mechanismsIntel ConfidentialDep
15、artment or Event Name8Embedded World China 20238DoE 1:Test ConfigurationTransmission ParametersTransmission ParametersValuesValuesTC TC QdiscQdiscTAPRIO QdiscMQPRIO QdiscETF QdiscNumber of Hardware Queues Number of Hardware Queues ConfiguredConfigured24Note:Hardware-dependent parameterTest Frame Siz
16、eTest Frame Size64B128B256BTest Packet NumbersTest Packet Numbers1000Cycle TimeCycle Time10ms20msNote:Depends on TC queue configurations.Advance Wakeup TimeAdvance Wakeup Time25 s(For TAPRIO only)Isochronous Window SizeIsochronous Window Size50 sGate schedule entryGate schedule entry5 msIntel Confid
17、entialDepartment or Event Name9Embedded World China 20239DoE I:Measurement PointsA A =Wakeup/Application latencyA A to B B=Transmit LatencyC C to D D=MAC LatencyD D to E E=Path delayIntel ConfidentialDepartment or Event Name10Embedded World China 202310DoE I:ResultsPacket Transmit Latency SummaryPac
18、ket Transmit Latency SummaryTAPRIO Higher frame incur value of 14us Max value of 40us Slightly higher delay MQPRIOMean value of 15us Require ETF deadline mode to ensure that data delivery is in time Intel ConfidentialDepartment or Event Name11Embedded World China 202311DoE I:Cycle Time Utilization f
19、or Packet TransferTransfer ConfigurationTransfer ConfigurationCycle Time Utilization in%Cycle Time Utilization in%Traffic Traffic Control TypeControl TypeNo.No.QueueQueueFrame Frame SizeSizeminminmaxmaxAverageAverageTAPRIOTAPRIO2640.050.3480.07521280.050.3430.06522560.0490.3280.0654640.0250.2750.037
20、41280.0260.1790.03842560.0250.1890.04MQPRIO MQPRIO with with Deadline Deadline ModeMode4640.030.1950.04241280.030.2310.04342560.030.2330.043Cycle Time Utilization Percentage is as is as low as 0.5%.low as setup_tc()4AFPACKET/AFINET(6)socketfor IT app5ptp4l uses AFPACKET socketfor passing timestamps6
21、AFXDP socket ZC mode offers direct DMA access with light-weight kernel buffer life cycle handling7libxdp offers ease-of-use API that interfaces with AFXDP socket interfaceIntel ConfidentialDepartment or Event Name15Embedded World China 202315TX FIFOTX MACTX DMA EngineCh7Ch6Ch1Ch0TASEthernetMAC Contr
22、ollerEthernet PHY4KB4KB4KB4KBGate Control ListGateGate IntervalInterval0 x80 125us0 x40 125us0 x20 125us0 x1F 125usTx Selection(Strict Priority)Data FabricCPUCPUCPUCPUSystem MemoryGfxOther System AgentKernel SpaceTXDescFrm1Frm2Frm3Frm64wireSystem Fabric Congestion Effects on TX2TX DMA OSP=1(Operate
23、Second Packet)allows Frm-2 TX frame to be DMA transferred ahead into TX MTL FIFO while Frm-1 TX frame is the midst of transmission out.1 After TX status of Frm-1 TX desc is updated,TX DMA engine starts the transfer of Frm-3 into TX MTL FIFO when Frm-2 is being transmitted out.13Frm1Frm22If system fa
24、bric congestion happens:The whole Frm-3 arrives late in TX MTL FIFO causing varying inter-packet gap on the wire.Tx frames in other MTL TX FIFO will be selected for transmission ahead of Frm-3 causing incorrect frame order.3Frm1Frm2Frm3TX directionvarying IPGFrm1Frm2Frm3Frm1TX directionIntel Confide
25、ntialDepartment or Event Name16Embedded World China 202316Varying Inter-Packet Gap Results(Wireshark)Frm1Frm2Frm3TX directionVarying IPGIntel ConfidentialDepartment or Event Name17Embedded World China 202317TX FIFOTX MACTX DMA EngineCh7Ch6Ch1Ch0TASEthernetMAC ControllerEthernet PHY4KB4KB4KB4KBGate C
26、ontrol ListGateGate IntervalInterval0 x80 125us0 x40 125us0 x20 125us0 x1F 125usTx Selection(Strict Priority)Data FabricCPUCPUCPUCPUSystem MemoryGfxOther System AgentKernel SpaceTXDescFrm1Frm2Frm3Frm64wireDeterministic Cyclic Transmission Enhancement AATX Time-Stamp updated through MAC register inst
27、ead of TX Descriptor.BBTX DMA engine can continuously fill TX MTL FIFO with more TX frames(within 4KB limit default)without waiting for TX status update by TX MAC.E.g.,64x64B,32x128B and 16x256B.CCWhen Qbv transmission gate opens,TX MAC transmits all TX frames in TX MTL FIFO at line-rate achieving o
28、ptimal IPG.DThrough cyclic full TX MTL FIFO buffering(TX status update disabled)and 802.1Qbv transmission gating control,we overcome the varying IPG issues caused by system fabric congestionFrm1Frm2Frm3Frm4Frm64|DIntel ConfidentialDepartment or Event Name18Embedded World China 202318Bounded and Very
29、 Low Inter-Packet Gap Results(Wireshark)Intel ConfidentialDepartment or Event Name19Embedded World China 202319Design of Experiment II:Setup and Tool IPG analysis Tool measures:i.i.Packet length Packet length of TX frames(of the same VLAN priority)sent in the same batch.ii.ii.Total number of TX fram
30、es Total number of TX frames(of the same VLAN priority)sent in the same batch.iii.iii.Number of transmit cycles Number of transmit cycles(of the same VLAN priority).iv.Relative position of start time start time and end time end time of the TX frames(of the same VLAN priority)sent in the same batch.v
31、.v.Five maximum values of inter-packet gap Five maximum values of inter-packet gap of TX frame according to their packet length and VLAN priorityUse PROFISHARK to capture cyclic packets transmitted.Example:2 traffic class cyclic traffics(64x64B via TXQ7+64x64B via TXQ6)for 100k loops will generate 1
32、GB pcap file.Intel ConfidentialDepartment or Event Name20Embedded World China 202320Design of Experiment II-IPG Measurement ToolDeveloped a Python script(scapyscapy lib)to analyze large size pcap file to measure cyclic traffic transmission IPG.Example of analysis reportExample of analysis reportCycl
33、ic Traffic Batch CharacterizationsMax 5 IPG values per frame size Max 5 Inter Packet Times per frame sizeTheoretical inter-packet timeIntel ConfidentialDepartment or Event Name21Embedded World China 202321Design of Experiment II:Result of OptimizationFrame CompositionFrame CompositionMAC PTP TX MAC
34、PTP TX timestamp+Qbvtimestamp+QbvPer-packet PTP TX Per-packet PTP TX timestamp+Qbvtimestamp+Qbv6 4 x 6 4 B T C 7 +6 4 x 6 4 B T C 7 +64x64BTC664x64BTC6208ns208ns4296ns32x128BTC7+32x128BTC7+32x128BTC632x128BTC6128ns128ns3560ns16x256BTC7+16x256BTC7+16x256BTC616x256BTC6120ns120ns2832ns8 x 5 1 2 B T C 7
35、 +8 x 5 1 2 B T C 7 +8x512BTC68x512BTC616ns16ns1712ns4x1024BTC7+4x1024BTC7+4x1024BTC64x1024BTC616ns16ns16ns3x1514BTC7 +3x1514BTC7 +3x1514BTC63x1514BTC616ns16ns16nsTx Frame Tx Frame IPGIPG for Mixed Packet Length for Mixed Packet LengthFrames CompositionFrames CompositionMAC PTP TX timestamp+QbvPer-p
36、acket PTP TX timestamp+Qbv43x64,128BTC-7+43x64,128BTC-7+43x64,128BTC-643x64,128BTC-6200ns4360ns25x64,256BTC-7+25x64,256BTC-7+25x64,256BTC-625x64,256BTC-6200ns4312ns15x64,512BTC-7+15x64,512BTC-7+15x64,512BTC-615x64,512BTC-6144ns5288ns7x64,1024BTC-7+7x64,1024BTC-7+7x64,1024BTC-67x64,1024BTC-616ns7176n
37、s5x64,1514BTC-7+5x64,1514BTC-7+5x64,1514BTC-65x64,1514BTC-616ns9232nsTx Frame Tx Frame IPGIPG for Fixed Packet Length for Fixed Packet LengthIntel ConfidentialDepartment or Event Name22Embedded World China 202322Conclusion IEC/IEEE 60820 and 3GPP standard define system level KPI w.r.t.to real-time a
38、nd cyclic traffic transmission.In Linux networking,QDisc and network stack processing introduces undesirable packet processing jitter that may not fulfil bounded and very low packet transmission jitter(micro-seconds cycle time).To meet micro-seconds cycle-time with bounded and very low TX jitter,we
39、need:-Linux Preempt-RT,Express Data Path Zero-Copy Driver-level optimization(e.g.TX PTP time-stamp through MAC register)and Linux system level tuning(gPTP TX time-stamp handling in driver,CPU/IRQ pinning,etc)We used Profishark and developed speciliazed Python/Scapy-based IPG analysis tool to confirm
40、 we have achieved 1us TX IPG under fixed and mixed frame length composition.Intel ConfidentialDepartment or Event Name23Embedded World China 2023232323Thank You for ListeningIntel ConfidentialDepartment or Event Name24Embedded World China 202324Legal DisclaimerINFORMATION IN THIS DOCUMENT IS PROVIDE
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